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SH7713 Scheda tecnica(PDF) 153 Page - Renesas Technology Corp |
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SH7713 Scheda tecnica(HTML) 153 Page - Renesas Technology Corp |
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153 / 904 page ![]() Section 3 DSP Operating Unit Rev.1.50 Aug. 30, 2006 Page 113 of 860 REJ09B0288-0150 PADD PINC PCMP DCF MOVX.W MOVX.W MOVX.W @R4+, @R5+R8, @R4, X0 X0 X1 MOVY.W MOVY.W [NOPY] @R6+, @R7+, Y0 Y1 A0, M1, M1, M0, A1 M0 A0 PMULS X0, Y0, M0 Figure 3.6 Sample Parallel Instruction Program [ ] mean that the contents can be omitted. The no operation instructions NOPX and NOPY can be omitted. For details on the B field in DSP data operation instructions, refer to section 3.6.4, DSP Operation Instructions. The DSR register condition code bit (DC) is always updated on the basis of the result of an unconditional ALU or shift operation instruction. Conditional instructions do not update the DC bit. Multiply instructions, also, do not update the DC bit. DC bit updating is performed by means of the CS[2:0] bits in the DSR register. The DC bit update rules are shown in table 3.19. |
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