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SH7713 Scheda tecnica(PDF) 157 Page - Renesas Technology Corp |
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SH7713 Scheda tecnica(HTML) 157 Page - Renesas Technology Corp |
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157 / 904 page ![]() Section 3 DSP Operating Unit Rev.1.50 Aug. 30, 2006 Page 117 of 860 REJ09B0288-0150 39 S 31 30 0 –28 to +28 – 2–31 39 S 32 31 0 –223 to +223 – 1 39 S S 31 30 16 15 16 15 0 –1 to +1 – 2–15 39 31 16 15 0 S 31 0 –215 to +215 – 1 16 15 31 22 0 –32 to +32 16 15 S 31 21 0 –16 to +16 16 15 S 31 30 0 –1 to +1 – 2–31 S 31 0 –231 to +231 – 1 DSP type fixed point With guard bits Without guard bits Multiplier input DSP type integer DSP type logical With guard bits CPU type integer S: Sign bit Longword : Binary point : Does not affect the operations Without guard bits Shift amount for arithmetic shift (PSHA) Shift amount for logical shift (PSHL) Figure 3.8 Data Formats The shift amount for the arithmetic shift (PSHA) instruction has a 7-bit field that can represent values from –64 to +63, but –32 to +32 are valid numbers for the instruction. Also the shift amount for a logical shift operation has a 6-bit field, but –16 to +16 are valid numbers for the instruction. The results when an invalid shift amount is specified cannot be guaranteed. |
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