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APPLICATION

5.1 Example of multi-line display

5-9

7220 Group User’s Manual

5.1.7 Set of multiple interrupts

(1)

When not setting multiple interrupts

When two or more interrupt requests occur at the same sampling point, the interrupt with the higher

priority (refer to “2.5 Interrupts, Table 2.5.1”) is received. This priority level is determined by

hardware but various priority processing by software can be executed using the interrupt enable bit

and each interrupt disable flag (I).

Assume, for example, that all interrupts (CRT, VSYNC, Timer 1) are enabled. When the multiple

interrupt is not set, these interrupt request bits are set to “1” and the interrupts are determined by

hardware as follows:

CRT interrupt

VSYNC interrupt

Timer 1 interrupt

Figure 5.1.8 shows the timing of interrupt processing when not setting multiple interrupts.

The I flag is set to “1” (all interrupts are disabled) automatically by hardware as soon as the interrupt

processing starts. Unless the I flag is cleared to “0,” other interrupt will not occur during the interrupt

processing.

Fig. 5.1.8 Timing of interrupt processing when not setting multiple interrupts

CRT interrupt request bit

VSYNC interrupt request bit

Timer 1 interrupt request bit

CRT interrupt processing

VSYNC interrupt processing

Timer 1 interrupt processing

Interrupt disable flag (I)

3’

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