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7220 Scheda tecnica(PDF) 243 Page - Renesas Technology Corp |
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7220 Scheda tecnica(HTML) 243 Page - Renesas Technology Corp |
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243 / 303 page  APPENDIX 6.6 SFR assignment 7220 Group User’s Manual 6-24 21716 21816 21916 21A16 21B16 b7 b0 RCR1 RCR0 Address Register ROM correction address 1 (high-order) Bit allocation s2 Page Register Area (addresses 21716 to 21B16) ROM correction address 1 (low-order) ROM correction address 2 (high-order) ROM correction address 2 (low-order) ROM correction enable register (RCR) : Fix this bit to “0” (do not write “1”) : < Bit allocation > Function bit : No function bit : Fix this bit to “1” (do not write “0”) Name : 1 0 ADL20 00 ADL21 ADL22 ADL23 ADL24 ADL25 ADL26 ADL27 ADH20 ADH21 ADH22 ADH23 ADH24 ADH25 ADH26 ADH27 ADL10 ADL11 ADL12 ADL13 ADL14 ADL15 ADL16 ADL17 ADH10 ADH11 ADH12 ADH13 ADH14 ADH15 ADH16 ADH17 Note: Only M37221M8-XXXSP and M37221MA-XXXSP have this area. Fig. 6.6.3 Memory map of 2 page register (including internal state immediately after reset and access characteristics) (3) (only M37221M8-XXXSP and M37221MA-XXXSP) |
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