M38K02FD datasheet(55/328 Pages) RENESAS

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FUNCTIONAL DESCRIPTION

Rev.2.00

Oct 05, 2006

page 38 of 112

38K0 Group

REJ09B0337-0200

HARDWARE

Fig. 42 Structure of EP00 control register 3

Control transfer completion

enable bit

Not used

CTENDE00

b7:b1

–

EP00 control register 3 (EP00CON3) [address 001C16]

0 : NAK transmission in the status stage

1 : Control transfer completion enabled (SIE transmits

NULL/ACK.) (valid in PID00 = “012”)

At reception of SETUP token:

This bit is cleared to “0” by the hardware.

Write “0” when writing.

“0” is read when reading.

–: State remaining

Bit name

Bit symbol

At reset

Function

H/W

S/W

USB function/Endpoint 0 buffer

ready interrupt bit

USB function/Endpoint 0 control

transfer completion interrupt bit

USB function/Endpoint 0 status

stage transition interrupt bit

USB function/Endpoint 0 SETUP

buffer ready interrupt bit

USB function/Endpoint 0 error

interrupt bit

Not used

BRDY00

CTEND00

CTSTS00

BSRDY00

ERR00

b7:b5

–

EP00 interrupt source register (EP00REQ) [address 001D16]

Bit name

Bit symbol

At reset

Function

H/W

S/W

0: No interrupt request issued

1: Interrupt request issued

This bit is set to “1” when the buffer is ready state

(enabled to be read/written) on USB function/Endpoint 0.

“0” can be set by software, but “1” cannot be set.

0: No interrupt request issued

1: Interrupt request issued

This bit is set to “1” when control transfer is completed

(NULL/ACK transmission in the status stage) on USB

function/Endpoint 0.

“0” can be set by software, but “1” cannot be set.

0: No interrupt request issued

1: Interrupt request issued

This bit is set to “1” when transition to status stage

occurs in CTENDE00 = “0” (control transfer completion

disabled) on USB function/Endpoint 0.

“0” can be set by software, but “1” cannot be set.

At transfer of control write:

When receiving IN-token in data stage (OUT)

At transfer of control read:

When receiving OUT-token in data stage (IN)

At no data transfer:

Nothing occurs.

0: No interrupt request issued

1: Interrupt request issued

This bit is set to “1” when the exclusive buffer for

SETUP is ready state (enabled to be read) on USB

function/Endpoint 0.

“0” can be set by software, but “1” cannot be set.

0: No interrupt request issued

1: Interrupt request issued

This bit is set to “1” when control transfer error occurs

on USB function/Endpoint 0.

This bit is cleared to “0” by the hardware when

receiving SETUP token.

“0” can be set by software, but “1” cannot be set.

Write “0” when writing.

“0” is read when reading.

–: State remaining

000

Fig. 43 Structure of EP00 interrupt source register

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