7477 datasheet(46/361 Pages) RENESAS

46 / 361 page

7470/7471/7477/7478 GROUP USER’S MANUAL

HARDWARE

1.10 I/O pins

1-39

Fig. 1.10.4 Structure of Ports P1 to P5 pull-up control register

b7 b6 b5 b4 b3 b2 b1 b0

Name

Function

At reset

R W

Ports P1 to P5 pull-up control register [Address

Ports P1 to P5 pull-up control register

0 : No pull-up

1 : Pull-up

Notes

Ports P10 to P13

pull-up control bit

Ports P40 to P43 pull-up

control bit

(Note 4)

Ports P24 to P27 pull-up

control bit

(Notes 2, 3)

Ports P20 to P23 pull-up

control bit

(Note 2)

Ports P14 to P17

pull-up control bit

1 : In the 7470/7477 group, the P1 to P4 Pull-up control register

is provided.

2 : In the 7477/7478 group, nothing is allocated to these bits.

They are undefined at reading.

3 : In the 7470/7477 group, nothing is allocated to these bits.

They are undefined at reading.

4 : The 7470/7477 group is provided with only

Nothing is allocated for this bit. This is write

disabled bit and is undefined at reading.

Nothing is allocated for this bit. This is write

disabled bit and is undefined at reading.

Ports P50 to P53 pull-up

control bit

(Note 3)

0 : No pull-up

1 : Pull-up

0 : No pull-up

1 : Pull-up

0 : No pull-up

1 : Pull-up

0 : No pull-up

1 : Pull-up

0 : No pull-up

1 : Pull-up

00D116]

P40 and P41.

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