3802 datasheet(13/208 Pages) RENESAS

13 / 208 page

3802 GROUP USER’S MANUAL

List of figures

Fig. 2.7.1 Example of Poweron reset circuit ........................................................................... 2-69

Fig. 2.7.2 RAM back-up system ................................................................................................. 2-69

CHAPTER 3 APPENDIX

Fig. 3.1.1 Circuit for measuring output switching characteristics ......................................... 3-13

Fig. 3.1.2 Timing diagram (in single-chip mode) ..................................................................... 3-14

Fig. 3.1.3 Timing diagram (in memory expansion mode and microprocessor mode) (1) .. 3-15

Fig. 3.1.4 Timing diagram (in memory expansion mode and microprocessor mode) (2) .. 3-16

Fig. 3.2.1 Power source current characteristic example ....................................................... 3-17

Fig. 3.2.2 Power source current characteristic example (in wait mode) ............................. 3-17

Fig. 3.2.3 Standard characteristic example of CMOS output port at P-channel drive(1) . 3-18

Fig. 3.2.4 Standard characteristic example of CMOS output port at P-channel drive(2) . 3-18

Fig. 3.2.5 Standard characteristic example of CMOS output port at N-channel drive(1) . 3-19

Fig. 3.2.6 Standard characteristic example of CMOS output port at N-channel drive(2) . 3-19

Fig. 3.2.7 A-D conversion standard characteristics ................................................................ 3-20

Fig. 3.2.8 D-A conversion standard characteristics ................................................................ 3-21

Fig. 3.3.1 Structure of interrupt control register 2 ................................................................. 3-22

Fig. 3.4.1 Wiring for the RESET pin ......................................................................................... 3-28

Fig. 3.4.2 Wiring for clock I/O pins ........................................................................................... 3-29

Fig. 3.4.3 Wiring for the VPP pin of the One Time PROM and the EPROM version ....... 3-29

Fig. 3.4.4 Bypass capacitor across the VSS line and the VCC line ..................................... 3-29

Fig. 3.4.5 Analog signal line and a resistor and a capacitor ............................................... 3-30

Fig. 3.4.6 Wiring for a large current signal line ..................................................................... 3-30

Fig. 3.4.7 Wiring to a signal line where potential levels change frequently ...................... 3-30

Fig. 3.4.8 Stepup for I/O ports ................................................................................................... 3-31

Fig. 3.4.9 Watchdog timer by software ..................................................................................... 3-31

Fig. 3.5.1 Structure of Port Pi (i=0, 1, 2, 3, 4, 5, 6)............................................................. 3-33

Fig. 3.5.2 Structure of Port Pi direction register (i=0, 1, 2, 3, 4, 5, 6) .............................. 3-33

Fig. 3.5.3 Structure of Transmit/Receive buffer register ....................................................... 3-34

Fig. 3.5.4 Structure of Serial I/O1 status register .................................................................. 3-34

Fig. 3.5.5 Structure of Serial I/O1 control register ................................................................. 3-35

Fig. 3.5.6 Structure of UART control register ......................................................................... 3-35

Fig. 3.5.7 Structure of Baud rate generator ............................................................................ 3-36

Fig. 3.5.8 Structure of Serial I/O2 control register ................................................................. 3-36

Fig. 3.5.9 Structure of Serial I/O2 register .............................................................................. 3-37

Fig. 3.5.10 Structure of Prescaler 12, Prescaler X, Prescaler Y ......................................... 3-37

Fig. 3.5.11 Structure of Timer 1 ................................................................................................ 3-38

Fig. 3.5.12 Structure of Timer 2, Timer X, Timer Y .............................................................. 3-38

Fig. 3.5.13 Structure of Timer XY mode register ................................................................... 3-39

Fig. 3.5.14 Structure of PWM control register ........................................................................ 3-40

Fig. 3.5.15 Structure of PWM prescaler ...................................................................................3-40

Fig. 3.5.16 Structure of PWM register ....................................................................................... 3-41

Fig. 3.5.17 Structure of AD/DA control register ...................................................................... 3-42

Fig. 3.5.18 Structure of A-D conversion register ..................................................................... 3-42

Fig. 3.5.19 Structure of D-A 1 conversion, D-A 2 conversion register ................................ 3-43

Fig. 3.5.20 Structure of Interrupt edge selection register ...................................................... 3-43

Fig. 3.5.21 Structure of CPU mode register ............................................................................. 3-44

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