TDA7476 datasheet(8/15 Pages) STMICROELECTRONICS

8 / 15 page

2C BUS INTERFACE

Data transmission from microprocessor to the

TDA7476 and viceversa takes place through the

2 wires I

2C BUS interface, consisting of the two

lines SDA and SCL (pull-up resistors to positive

supply voltage must be connected).

Data Validity

As shown by fig. 2, the data on the SDA line must

be stable during the high period of the clock. The

HIGH and LOW state of the data line can only

change when the clock signal on the SCL line is

LOW.

Start and Stop Conditions

As shown by fig. 3 a start condition is a HIGH to

LOW transition of the SDA line while SCL is

HIGH. The stop condition is a LOW to HIGH tran-

sition of the SDA line while SCL is HIGH.

Byte Format

Every byte transferred to the SDA line must con-

tain 8 bits. Each byte must be followed by an ac-

knowledge bit. The MSB is transferred first.

Acknowledge

The transmitter* puts a resistive HIGH level on the

SDA line during the acknowledge clock pulse (see

fig.4). The receiver** the acknowledges has to pull-

down (LOW) the SDA line during the acknowledge

clock pulse, so that the SDAline is stable LOW dur-

ing this clock pulse.

* Transmitter

= master (

µP) when it writes an address to

the TDA7476

= slave (TDA7476) when the

µP reads a

data byte from TDA7476

** Receiver

= slave (TDA7476) when the

µP writes an

address to the TDA7476

= master (

µP) when it reads a data byte from

TDA7476

Figure 2: Data Validity on the I

2CBUS

Figure 3: Timing Diagram on the I

2CBUS

Figure 4: Acknowledge on the I

2CBUS

TDA7476

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