TDA8204B datasheet(6/12 Pages) STMICROELECTRONICS

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4 - Interchip Bus

A one-line serial bus provides interchip communi-

cations allowing control of all functions through the

single I

2C bus interface.

5 - I

2C Bus

An I

2C bus interface provides access to control and

status registers within the two chips to allow control

of their functions and monitoring of status. A digital

filter is included to improve noise immunity.

5.1 - DATA FLAGS (see Figure 4)

These indicate the status of the descrambled data

on the DDO pin. They are inhibited if the decoder

is out of alignement.

- FID : Frame alignment word (scrambled)

- PDV : Parity Data Valid. CIB0 and CIB1 overwrite

the first 2 bits of FAW

- ADV : 11 additional data bits

- DV : Data valid (mode dependant)

5.2 - DECRYPTION (see Figure 5)

The PRBS generator (used for descrambling) is

normally preset to all ones at the start of each

frame. However, it is possible to preset it to any

value on each frame by means of a code word clock

(CWC) and serial code word data (CWD) interface

on pins SEL0 and SEL1.

CWD, which is clocked in on the negative going

edges of the CWC clock, can be sent anywhere

during the frame except when FID = 1. The CWC

is asynchronous with respect to the Nicam clock

and the CWD will be used on the following frame.

During the time FID = 1, the levels on the SEL0,

SEL1 pins are read for language selection. Code

words for descrambler presetting may be sent in

either an 8-bit or 9-bit formats. There are four

possibilities :

- if 7 or less clock cycles are counted on CW-clock

during a frame, the PRBS generator is preset to

all ones ;

- if 8 clock cycles are counted, 8 bits of CW-data

are clocked into the shift register, the first bit of the

previous transfer now moving to bit 9 position in

the shift register. The resulting value is used to

preset the PRBS generator on the next frame.

- if 9 clock cycles are counted, the CW-data (which

has been clocked into a 9-bit shift register) is used

to preset the PRBS generator on the next frame.

- if 10 or more clock cycles are counted, only the

first 9 bits of the CW-data are used and loaded

into the PRBS generator on the next frame.

CK728

DDO

FID

PDV

ADV

DV Stereo

DV Data

DV Mono

CB0 CB1

C0 C1 C2 C3 C4 AD0

AD10

NICAM DATA 704 BITS

24 CONTROL

704 DATA

EVEN FRAME

ODD FRAME

1 FRAME

NEXT FRAME

FA W

Figure 4 : Data Flags

FID

SEL0

(CWC)

SEL1

(CWD)

Figure 5 : PRBS Presetter

TDA8204B

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