TS68230CFN8 datasheet(54/61 Pages) STMICROELECTRONICS

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6.6. AC ELECTRICAL SPECIFICATIONS

(VCC = 5.0Vdc ± 5%, VSS = 0Vdc, TA =TL to TH unless otherwise noted)

Peripheral Output Timings (figures 6.5)

8MHz

10MHz

Number

Parameter

Min.

Max.

Min.

Max.

Unit

Handshake Input H1(H4) Pulse Width Asserted

Handshake Input H1(H4) Pulse Width Negated

H1(H3) Asserted to H2(H4) Negated (delay time)

150

120

CLK Low to H2(H4) Asserted (delay time)

100

(1 )

H2(H4) Asserted to H1(H3) Asserted

(2 )

CLK Low to H2(H4) Pulse Negated (delay time)

125

(3 . 4 )

Synchronized H1(H3) to CLK low on which DMAREQ is asserted

2.5

3.5

2.5

3.5

CLK Per

CLK low on which DMAREQ is asserted to CLK low on which

DMAREQ is negated

2.5

CLK Per

CLK Low to Port Output Data Valid (delay time) (modes 0 and 1)

150

120

(3 . 4 )

Synchronized H1(H3) to Port Output Data Invalid (modes 0 and 1)

1.5

2.5

1.5

2.5

CLK Per

H1 Negated to Port Output Data Valid (modes 2 and 3)

H1 Asserted to Port Output Data High Impedance (modes 2 and 3)

(5 )

H1(H3) Asserted to CLK High (setup time)

CLK Low to DMAREQ Low (delay time)

120

100

CLK Low to DMAREQ High (delay time)

120

100

2. This specification applies only when a pulsed handshake option is chosen and the pulse is not shortened due to an

early asserted edge of H1(H3).

3. The maximum value is caused by a peripheral access (H1(H3) asserted) and bus access (CS asserted) occurring

at the same time.

4. Syncrhonized means that the input signal has been seen by the PI/T on the appropriate edge of the clock (rising

edge for H1(H3) and falling edge for CS). (Refer to the 1.4 Bus Interface Operation for the exception concerning

CS).

5. If the setup time on the rising edge of the clock is not met, H1(H3) may not be recognized until the next rising of

the clock.

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