MPC8640 datasheet(41/140 Pages) FREESCALE

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MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

Ethernet Management Interface Electrical Characteristics

Figure 21 provides the AC test load for eTSEC.

Figure 21. eTSEC AC Test Load

Figure 22 shows the RMII receive AC timing diagram.

Figure 22. RMII Receive AC Timing Diagram

Ethernet Management Interface Electrical

Characteristics

The electrical characteristics specified here apply to MII management interface signals MDIO

(management data input/output) and MDC (management data clock). The electrical characteristics for

GMII, RGMII, RMII, TBI and RTBI are specified in “Section 8, “Ethernet: Enhanced Three-Speed

Ethernet (eTSEC), MII Management.”

RXD[1:0], CRS_DV, RX_ER hold time to REF_CLK

rising edge

tRMRDX

2.0

—

Note:

1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)

(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example,

tMRDVKH symbolizes MII receive timing (MR) with respect to the time data input signals (D) reach the valid state (V)

relative to the tMRX clock reference (K) going to the high (H) state or setup time. Also, tMRDXKL symbolizes MII

receive timing (GR) with respect to the time data input signals (D) went invalid (X) relative to the tMRX clock

reference (K) going to the low (L) state or hold time. Note that, in general, the clock reference symbol representation

is based on three letters representing the clock of a particular functional. For example, the subscript of tMRX

represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate

letter: R (rise) or F (fall).

Table 36. RMII Receive AC Timing Specifications (continued)

At recommended operating conditions with L/TVDD of 3.3 V ± 5%.

Parameter/Condition

Symbol 1

Min

Typ

Max

Unit

Output

Z0 = 50 Ω

LVDD/2

RL = 50 Ω

REF_CLK

RXD[1:0]

tRMRDX

tRMR

tRMRH

tRMRR

tRMRF

CRS_DV

RX_ER

tRMRDV

Valid Data

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