MPC5565 datasheet(2/54 Pages) FREESCALE

2 / 54 page

MPC5565 Microcontroller Data Sheet, Rev. 2.0

Overview

Freescale Semiconductor

The MPC5500 family of parts contains many new features coupled with high performance CMOS

technology to provide significant performance improvement over the MPC565.

The host processor core of the MPC5565 also includes an instruction set enhancement allowing variable

length encoding (VLE). This allows optional encoding of mixed 16- and 32-bit instructions. With this

enhancement, it is possible to significantly reduce the code size footprint.

The MPC5565 has two levels of memory hierarchy. The fastest accesses are to the 8-kilobytes (KB)

unified cache. The next level in the hierarchy contains the 80-KB on-chip internal SRAM and

two-megabytes (MB) internal flash memory. The internal SRAM and flash memory hold instructions and

data. The external bus interface is designed to support most of the standard memories used with the

MPC5xx family.

The complex input/output timer functions of the MPC5565 are performed by an enhanced time processor

unit (eTPU) engine. The eTPU engine controls 32 hardware channels. The eTPU has been enhanced over

the TPU by providing: 24-bit timers, double-action hardware channels, variable number of parameters per

channel, angle clock hardware, and additional control and arithmetic instructions. The eTPU is

programmed using a high-level programming language.

The less complex timer functions of the MPC5565 are performed by the enhanced modular input/output

system (eMIOS). The eMIOS’ 24 hardware channels are capable of single-action, double-action,

pulse-width modulation (PWM), and modulus-counter operations. Motor control capabilities include

edge-aligned and center-aligned PWM.

Off-chip communication is performed by a suite of serial protocols including controller area networks

(FlexCANs), enhanced deserial/serial peripheral interfaces (DSPIs), and enhanced serial communications

interfaces (eSCIs). The DSPIs support pin reduction through hardware serialization and deserialization of

timer channels and general-purpose input/output (GPIOs) signals.

The MCU has an on-chip enhanced queued dual analog-to-digital converter (eQADC). The 324 package

has 40-channels.

The system integration unit (SIU) performs several chip-wide configuration functions. Pad configuration

and general-purpose input and output (GPIO) are controlled from the SIU. External interrupts and reset

control are also determined by the SIU. The internal multiplexer submodule provides multiplexing of

eQADC trigger sources, daisy chaining the DSPIs, and external interrupt signal multiplexing.

MPC5565 Scheda tecnica(PDF) 2 Page - Freescale Semiconductor, Inc