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LPC2158 Scheda tecnica(PDF) 35 Page - NXP Semiconductors |
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LPC2158 Scheda tecnica(HTML) 35 Page - NXP Semiconductors |
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35 / 45 page ![]() LPC2157_2158_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 15 October 2008 35 of 45 NXP Semiconductors LPC2157/2158 Single-chip 16-bit/32-bit microcontrollers [1] The ADC is monotonic, there are no missing codes. [2] The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 7. [3] The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. See Figure 7. [4] The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the ideal curve. See Figure 7. [5] The gain error (EG) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset error, and the straight line which fits the ideal transfer curve. See Figure 7. [6] The absolute error (ET) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated ADC and the ideal transfer curve. See Figure 7. [7] See Figure 8. Table 8. ADC static characteristics VDDA = 2.5 V to 3.6 V; Tamb = −40 °C to +85 °C unless otherwise specified; ADC frequency 4.5 MHz. Symbol Parameter Conditions Min Typ Max Unit VIA analog input voltage 0 - VDDA V Cia analog input capacitance - - 1 pF ED differential linearity error VSSA =0V, VDDA = 3.3 V [1][2] -- ±1 LSB EL(adj) integral non-linearity VSSA =0V, VDDA = 3.3 V [3] -- ±2 LSB EO offset error VSSA =0V, VDDA = 3.3 V [4] -- ±3 LSB EG gain error VSSA =0V, VDDA = 3.3 V [5] -- ±0.5 % ET absolute error VSSA =0V, VDDA = 3.3 V [6] -- ±4 LSB Rvsi voltage source interface resistance [7] --40 k Ω |
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