6

4378CS–AVR–09/08

AT90PWM1

4.1

Block Diagram

Figure 4-1.

Block Diagram

The AVR core combines a rich instruction set with 32 general purpose working registers. All the

32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent

registers to be accessed in one single instruction executed in one clock cycle. The resulting

architecture is more code efficient while achieving throughputs up to ten times faster than con-

ventional CISC microcontrollers.

The AT90PWM1 provides the following features: 8K bytes of In-System Programmable Flash

with Read-While-Write capabilities, 512 bytes EEPROM, 512 bytes SRAM, 53 general purpose

I/O lines, 32 general purpose working registers, 2 Power Stage Controllers, two flexible

Timer/Counters with compare modes and PWM, an 8-channel 10-bit ADC with two differential