DS564F2

17

CS5341

Confidential Draft

3/11/08

4.2.3

Master Clock

The CS5341 requires a Master clock (MCLK) which runs the internal sampling circuits and digital filters.

There is also an internal MCLK divider which is automatically activated based on the speed mode and

frequency of the MCLK. Table 3 shows a listing of the external MCLK/LRCK ratios that are required.

Table 4 lists some common audio output sample rates and the required MCLK frequency. Please note

that not all of the listed sample rates are supported when operating with a fast MCLK (512x, 256x, 128x

for Single-, Double-, and Quad-Speed Modes, respectively).

4.3

Serial Audio Interface

The CS5341 supports both I²S and Left-Justified serial audio formats. Upon start-up, the CS5341 will detect

the logic level on SDOUT (pin 4). A 10 k

Ω pull-up to VL is needed to select I²S format, and a 10 kΩ pull-

down to GND is needed to select Left-Justified format. Figures 19 and 20 illustrate the I²S and Left-Justified

audio formats. Please see Figures 13 through 16, for more information on the required timing for the two

serial audio interface formats. Also see Application Note AN282 for a detailed discussion of the serial audio

interface formats.

Single-Speed Mode

Double-Speed Mode

Quad-Speed Mode

MCLK/LRCK Ratio

256x, 512x

128x, 256x

64x*,128x

* Quad Speed, 64x only available in Master Mode.

Table 3. Master Clock (MCLK) Ratios

SAMPLE RATE (kHz)

MCLK (MHz)

32

8.192

44.1

11.2896

22.5792

48

12.288

24.576

64

8.192

88.2

11.2896

22.5792

96

12.288

24.576

192

12.288

24.576

Table 4. Master Clock (MCLK) Frequencies for Standard Audio Sample Rates

SD A T A

2 3 2 2

8

7

23 22

SCLK

LR C K

23 2 2

65

43

21

0

87

65

43

21

0

9

9

Left C hann el

R igh t C h a nne l

Figure 19. I²S Serial Audio Interface

SD AT A

2 3 2 2

7

6

23 2 2

SC L K

L RCK

23 22

54

32

10

8

76

54

32

10

8

9

9

Le ft C h a n nel

R igh t C h annel

Figure 20. Left-Justified Serial Audio Interface