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USB6B1RL Scheda tecnica(PDF) 2 Page - STMicroelectronics |
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USB6B1RL Scheda tecnica(HTML) 2 Page - STMicroelectronics |
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2 / 9 page ![]() USB6Bx 2/9 Fig. A1 : Lw VI/O ESD SURGE GND I/O +Vcc Vf Lw di dt Lw di dt Vcl+ = Vcc+Vf+ Lw di dt surge >0 -Vf- Lw di dt surge <0 Vcl- = t tr=1ns Vcc+Vf Lw di dt Vcl+ POSITIVE SURGE -Lw di dt t tr=1ns -Vf Vcl- NEGATIVE SURGE The USB6Bx is particularly optimized to perform surge protection based on the rail to rail topology. The clamping voltage VCL can be estimated as follow: VCL+=Vcc+VF for positive surges VCL -=-VF for negative surges with: VF =Vt + rd.Ip (VF forward drop voltage) / (Vt forward drop threshold voltage) Note: the estimations do not take into account phenomena due to parasitic inductances. SURGE PROTECTION TECHNICAL INFORMATION |
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