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EPLD Scheda tecnica(PDF) 16 Page - Altera Corporation

Il numero della parte EPLD
Spiegazioni elettronici  The Altera Classic device family offers a solution to high-speed, lowpower logic integration. Fabricated on advanced CMOS technology
PDF  42 Pages
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Produttore elettronici  ALTERA [Altera Corporation]
Homepage  http://www.altera.com
Logo ALTERA - Altera Corporation

EPLD Scheda tecnica(HTML) 16 Page - Altera Corporation

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Altera Corporation
Classic EPLD Family Data Sheet
Notes to tables:
(1)
See the Operating Requirements for Altera Devices Data Sheet in this data book.
(2)
Numbers in parentheses are for industrial-temperature-range devices.
(3)
The minimum DC input is –0.3 V. During transitions, the inputs may undershoot to –2.0 V (EP610) or
–0.5 V (EP610I) or overshoot to 7.0 V (EP610) or VCC + 0.5 V (EP610I) for input currents less than 100 mA and periods
less than 20 ns.
(4)
For EP610 devices, maximum VCC rise time is 50 ms. For EP610I devices, maximum VCC rise time is unlimited with
monotonic rise.
(5)
For EP610-15 and EP610-20 devices: tR and tF = 40 ns.
For EP610-15 and EP610-20 clocks: tR and tF = 20 ns.
(6)
These values are specified in Table 3 on page 758.
(7)
The IOH parameter refers to high-level TTL or CMOS output current; the IOL parameter refers to low-level TTL
output current.
(8)
This parameter does not apply to EP610I devices.
(9)
The device capacitance is measured at 25
° C and is sample-tested only.
(10) Typical values are for TA = 25° C and VCC = 5 V.
(11) When the Turbo Bit option is not set (non-Turbo mode), EP610 devices enter standby mode if no logic transitions
occur for 100 ns after the last transition. When the Turbo Bit option is not set, EP610I devices enter standby mode if
no logic transitions occur for 75 ns after the last transition.
(12) Measured with a device programmed as a 16-bit counter.



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