2007

V0.28P

-10-

F75133

8. Register Description

8.1 Control Register

 Index 00h

Bit

Name

R/W Default

Description

7

INIT

R/W

0

Soft ware reset device, if write 1 to this bit will reset this IC and then it will auto

clear to 0.

6-5 Reserved.

R/W

0

Reserved

4

CLK_SEL

R/W

0

Set to 1 the output clock frequency will select to 50HZ, the default frequency is

100HZ. User can select clock duty cycle from CR06 bit 7~4

3-1 MONITOR_TIME

R/W

100

Set these bits to decide how many time to be one monitor cycle, and after one

cycle finish, it will auto update average duty to PWM duty register (CR02).

000: (About 8.858 Sec)

001: (About 4.429 Sec)

010: (About 2.215 Sec)

011: (About 1.107 Sec)

100: (About 0.554 Sec) (Default value)

101: (About 0.277 Sec)

110: (About 0.138 Sec)

111: (About 0.069 Sec)

0

POWER_DOWN

R/W

0

Set to 1 to stop PWM duty monitor and power down this IC.

8.2 Pins Control Register

 Index 01h

Bit

Name

R/W Default

Description

7

INV_TURBO

R/W

0

If set this bit to1, invert TURBO# pin output polarity.

6

INV_FAULT

R/W

0

If set this bit to1, invert FAULT# pin output polarity.

5

INV_PME

R/W

0

If set this bit to1, invert PME# pin output polarity.