XIO2000AI datasheet(114/159 Pages) TAOS

114 / 159 page

PCI Express Extended Configuration Space

104

April 2007 Revised October 2008

SCPS155C

5.10 Secondary Uncorrectable Error Status Register

The secondary uncorrectable error status register reports the status of individual PCI bus errors as they occur.

Software may only clear these bits by writing a 1b to the desired location. See Table 5−8 for a complete

description of the register contents.

PCI Express extended register offset:

12Ch

Read-only, Read/Clear

Default value:

0000 0000h

BIT NUMBER

RESET STATE

BIT NUMBER

RESET STATE

Table 5−8. Secondary Uncorrectable Error Status Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

31:14

RSVD

Reserved. Returns 00 0000 0000 0000 0000b when read.

13†

BRIDGE_ERROR

Internal bridge error. This error bit is associated with a PCI-X error and returns 0b when read.

12†

SERR_DETECT

RCU

SERR assertion detected. This bit is asserted when the bridge detects the assertion of SERR

on the secondary bus.

11†

PERR_DETECT

RCU

PERR assertion detected. This bit is asserted when the bridge detects the assertion of PERR

on the secondary bus.

10†

DISCARD_TIMER

RCU

Delayed transaction discard timer expired. This bit is asserted when the discard timer expires

for a pending delayed transaction that was initiated on the secondary bus.

9†

UNCOR_ADDR

RCU

Uncorrectable address error. This bit is asserted when the bridge detects a parity error during

the address phase of an upstream transaction.

8†

ATTR_ERROR

Uncorrectable attribute error. This error bit is associated with a PCI-X error and returns 0b

when read.

7†

UNCOR_DATA

RCU

Uncorrectable data error. This bit is asserted when the bridge detects a parity error during a

data phase of an upstream write transaction, or when the bridge detects the assertion of

PERR when forwarding read completion data to a PCI device.

6†

SC_MSG_DATA

Uncorrectable split completion message data error. This error bit is associated with a PCI-X

error and returns 0b when read.

5†

SC_ERROR

Unexpected split completion error. This error bit is associated with a PCI-X error and returns

0b when read.

RSVD

Reserved. Returns 0b when read.

3†

MASTER_ABORT

RCU

Received master abort. This bit is asserted when the bridge receives a master abort on the

PCI interface.

2†

TARGET_ABORT

RCU

Received target abort. This bit is asserted when the bridge receives a target abort on the PCI

interface.

1†

SC_MSTR_ABORT

Master abort on split completion. This error bit is associated with a PCI-X error and returns 0b

when read.

RSVD

Reserved. Returns 0b when read.

† These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.

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