XIO2000AI datasheet(123/159 Pages) TAOS

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PCI Express Extended Configuration Space

113

April 2007 Revised October 2008

SCPS155C

5.22 VC Resource Control Register (VC0)

The VC resource control register for VC0 allows software to control VC0 and the associated port and

arbitration schemes supported by the bridge. See Table 5−18 for a complete description of the register

contents.

PCI Express extended register offset:

164h

Read-only, Read/Write

Default value:

8000 00FFh

BIT NUMBER

RESET STATE

BIT NUMBER

RESET STATE

Table 5−18. VC Resource Control Register (VC0) Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

VC_EN

VC enable. This field is internally hardwired to 1b to indicate that this VC resource is always

enabled.

30:27

RSVD

Reserved. Returns 0h when read.

26:24

VC_ID

Virtual channel ID. This field is internally hardwired to 000b to indicate that this VC resource

is always used for VC0.

23:20

RSVD

Reserved. Returns 0h when read.

19:17

PORT_ARB_SELECT

Port arbitration select. This read-only field returns 000b when read, because only

hardware-fixed, round-robin arbitration is supported for this VC.

LOAD_PORT_TABLE

Load port arbitration table. This read-only bit returns 0b when read, because no port

arbitration table is supported for this VC.

15:8

RSVD

Reserved. Returns 00h when read.

7:0

TC_VC_MAP

TC/VC map. This field indicates all of the traffic classes that are mapped to this VC. A 1b in

any bit position indicates that the corresponding traffic class is enabled for this VC. A 0b

indicates that the corresponding traffic class is mapped to a different VC. The following table

is used:

Bit 0 = Traffic class 0 (This bit is read-only and returns a value of 1b)

Bit 1 = Traffic class 1

Bit 2 = Traffic class 2

Bit 3 = Traffic class 3

Bit 4 = Traffic class 4

Bit 5 = Traffic class 5

Bit 6 = Traffic class 6

Bit 7 = Traffic class 7

The default value of FFh indicates that all eight traffic classes are initially mapped to VC0.

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