XIO2000AI datasheet(141/159 Pages) TAOS

141 / 159 page

Memory-Mapped TI Proprietary Register Space

131

April 2007 Revised October 2008

SCPS155C

Table 6−13. Serial IRQ Edge Control Register Description (Continued)

BIT

FIELD NAME

ACCESS

DESCRIPTION

3†

IRQ3_MODE

IRQ 3 edge mode

0 = Edge mode (default)

1 = Level mode

2†

IRQ2_MODE

IRQ 2 edge mode

0 = Edge mode (default)

1 = Level mode

1†

IRQ1_MODE

IRQ 1 edge mode

0 = Edge mode (default)

1 = Level mode

0†

IRQ0_MODE

IRQ 0 edge mode

0 = Edge mode (default)

1 = Level mode

† These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.

6.25 Serial IRQ Status Register

This register indicates when a level mode IRQ is signaled on the serial IRQ stream. After a level mode IRQ

is signaled, a write-back of 1b to the asserted IRQ status bit re-arms the interrupt. IRQ interrupts that are

defined as edge mode in the serial IRQ edge control register are not reported in this status register.

This register is an alias for the serial IRQ status register in the classic PCI configuration space (offset E4h,

see Section 4.74). See Table 6−14 for a complete description of the register contents.

Device control memory window register offset:

4Ch

Read/Clear

Default value:

0000h

BIT NUMBER

RESET STATE

Table 6−14. Serial IRQ Status Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

IRQ15

RCU

IRQ 15 asserted. This bit indicates that the IRQ has been asserted.

0 = Deasserted

1 = Asserted

IRQ14

RCU

IRQ 14 asserted. This bit indicates that the IRQ has been asserted.

0 = Deasserted

1 = Asserted

IRQ13

RCU

IRQ 13 asserted. This bit indicates that the IRQ has been asserted.

0 = Deasserted

1 = Asserted

IRQ12

RCU

IRQ 12 asserted. This bit indicates that the IRQ has been asserted.

0 = Deasserted

1 = Asserted

IRQ11

RCU

IRQ 11 asserted. This bit indicates that the IRQ has been asserted.

0 = Deasserted

1 = Asserted

IRQ10

RCU

IRQ 10 asserted. This bit indicates that the IRQ has been asserted.

0 = Deasserted

1 = Asserted

IRQ9

RCU

IRQ 9 asserted. This bit indicates that the IRQ has been asserted.

0 = Deasserted

1 = Asserted

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