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AX2000-1CS896 Scheda tecnica(PDF) 73 Page - Actel Corporation |
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AX2000-1CS896 Scheda tecnica(HTML) 73 Page - Actel Corporation |
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73 / 226 page  Axcelerator Family FPGAs v2.7 2-59 Global Resource Distribution At the root of each global resource is a PLL. There are two groups of four PLLs for every device. One group, located at the center of the north edge (in the I/O ring) of the chip, sources the four HCLKs. The second group, located at the center of the south edge (again in the I/O ring), sources the four CLKs (Figure 2-38). Regardless of the type of global resource, HCLK or CLK, each of the eight resources reach the ClockTileDist (CTD) Cluster located at the center of every core tile with zero skew. From the ClockTileDist Cluster, all four HCLKs and four CLKs are distributed through the core tile (Figure 2- 39). Figure 2-38 • PLL Group Figure 2-39 • Example of HCLK and CLK Distributions on the AX2000 PLL Cluster PLL Cluster PN P N P N P N PN P N P N P N HCLKA HCLKB HCLKC HCLKD CLKE PLL CLKF CLKG CLKH PLL PLL PLL PLL PLL PLL PLL PLL Group HCLK CLK PLL Group 4 4 ClockTileDist Cluster |
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