LTC1402IGN datasheet(16/24 Pages) LINER

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LTC1402

DIGITAL INTERFACE

The LTC1402 has a 3-wire SPI (Serial Protocol Interface)

interface. The SCK and CONV inputs and DOUT output

implement this interface. The SCK and CONV inputs are TTL

compatible and also accept swings from 3V or 5V logic. The

amplitude of DOUT can easily produce 5V logic or 3V logic

swings by tying the independent output supply OVDD

(Pin 11) to the same supply as system logic. A detailed de-

scription of the three serial port signals follows.

CONV at Pin 16

The rising edge of CONV starts a conversion but subse-

quent rising edges at CONV, during the following 14 SCK

cycles of conversion, are ignored by the LTC1402. The

duty cycle of CONV can be arbitrarily chosen to be used as

a frame sync signal for the processor serial port. A simple

approach to generate CONV is to create a pulse that is one

SCK wide to drive the LTC1402 and then buffer this signal

with the appropriate number of inverters to drive the frame

sync input of the processor serial port. It is good practice

to drive the LTC1402 CONV input first to avoid digital noise

interference during the sample-to-hold transition triggered

by CONV at the start of conversion. Another point to con-

sider is the level of jitter in the CONV signal if the input

signals have fast transients or sinewaves. Some proces-

sors can be programmed to generate a convenient frame

sync pulse at their serial port, but often this signal is de-

rived from a jittery processor phase locked loop clock

multiplier. This is true even if a low jitter crystal clock is the

reference for the processor clock multiplier.

SCK at Pin 15

The rising edge of SCK advances the conversion process

and also udpates each bit in the DOUT data stream. After

CONV rises, the second rising edge of SCK sends out the

REFREADY bit. Subsequent edges send out the 12 data

bits, with the MSB sent first. A simple approach is to

generate SCK to drive the LTC1402 and then buffer this

signal with the appropriate number of inverters to drive the

serial clock input of the processor serial port. The rising

edge of SCK is guaranteed to coincide with stable data at

DOUT. It is good practice to drive the LTC1402 SCK input

first to avoid digital noise interference during the internal

bit comparison decision by the internal high speed com-

parator. Unlike the CONV input, the SCK input is not

sensitive to jitter because the input signal is already

sampled and held constant.

DOUT at Pin 10

Upon power-up, the DOUT output is automatically reset to

the high impedance state. The DOUT output remains in high

impedance until a new conversion is started. DOUT sends

out 13 bits in the output data stream after the second rising

edge of SCK after the start of conversion with the rising

APPLICATIONS INFORMATION

15mW. The internal reference remains powered in Nap

mode. One or more rising edges at SCK wake up the

LTC1402 for service very quickly, and CONV can start an

accurate conversion within a clock cycle. Four rising edges

at CONV, without any intervening rising edges at SCK, put

the LTC1402 in Sleep mode and the power drain drops

from 90mW to 10

µW. One or more rising edges at SCK

wake up the LTC1402 for operation. The internal reference

(VREF) takes 2ms to slew and settle with a 10µF load, and

the REFREADY bit in the DOUT stream takes an additional

10ms to go high after the reference output Pin 5 (VREF) has

finished slewing. Note that, using sleep mode more fre-

quently than every 2ms, compromises the settled accu-

racy of the internal reference. Figure 12 shows the power

consumption versus the conversion rate. Note that, for

slower conversion rates, the Nap and Sleep modes can be

used for substantial reductions in power consumption.

Figure 12. Power Consumption vs Sample Rate

in Normal Mode, Nap Mode and Sleep Mode

SAMPLE RATE (MHz)

0.01

0.1

0.01

0.1

1402 F12

0.001

100

VDD CURRENT

DUAL

±5V

VSS CURRENT

DUAL

±5V

VDD CURRENT

SINGLE 5V

VSS CURRENT

SINGLE 5V

VDD CURRENT

SLEEP MODE

VDD CURRENT

NAP MODE

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