LTC3706IGN datasheet(7/20 Pages) LINER

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LTC3706

3706fb

PIN FUNCTIONS

SG (Pin 1): Gate Drive for the “Synchronous” MOSFET.

FG (Pin 2): Gate Drive for the “Forward” MOSFET.

PGOOD (Pin 3): Open-Drain Power Good Output. The FB

pin is monitored to ensure that the output is in regulation.

When the output is not in regulation, the PGOOD pin is

pulled low.

MODE (Pin 4): Tie to either GND or VCC to set the maxi-

mum duty cycle at either 50% or 75% respectively. Tie to

ground through either a 200k or 100k resistor (50% or

75% maximum duty cycle) to disable pulse encoding. In

this mode, normal PWM signals will be generated at the

PT+ pin, while a clock signal is generated at the PT– pin.

PHASE (Pin 5): Control Input to the Phase Selector. This

pin determines the phasing of the controller CLK relative

to the synchronizing signal at the FS/SYNC pin.

FB (Pin 6): The Inverting Input of the Main Loop Error

Ampliﬁer.

ITH (Pin 7): The Output of the Main Loop Error Ampliﬁer.

Place compensation components between the ITH pin

and GND.

RUN/SS (Pin 8): Combination Run Control and Soft-Start

Inputs. A capacitor to ground sets the ramp time of the

output voltage. Holding this pin below 0.4V causes the IC

to shut down all internal circuitry.

VSOUT, VS+, VS– (Pins 9, 10, 11): VSOUT is the output of

a precision, unity-gain differential ampliﬁer. Tie VS+ and

VS– to the output of the main DC/DC converter to achieve

true remote differential sensing. This allows DCR error

effects to be minimized.

GND (Pin 12): Signal Ground.

FS/SYNC (Pin 13): Combination Frequency Set and SYNC

pin. Tie to GND or VCC to run at 200kHz and 300kHz

respectively. Place a single resistor to ground at this pin

to set the frequency between 100kHz and 500kHz. To

synchronize, drive this pin with a clock signal to achieve

PLL synchronization from 75kHz to 500kHz. Sources

20μA of current.

SLP (Pin 14): Slope Compensation Input. Place a single

resistor to ground to set the desired amount of slope

compensation.

IS– (Pin 15): Negative Input to the Current Sense Circuit.

When using current sense transformers, this pin may be

tied to VCCforsingle-endedsensingwitha1.28Vmaximum

current trip level.

IS+ (Pin 16): Positive Input to the Current Sense Circuit.

Connect to the positive end of a current sense resistor or

to the output of a current sense transformer.

REGSD(Pin17):Thispinisusedtopreventoverheatingofthe

external linear regulator pass device that generates the VCC

supply voltage from the VIN voltage. A current proportional

to the voltage across the external pass device ﬂows out of

this pin. The IC shuts down the linear regulator when the

voltage on this pin exceeds 4V. Place a resistor (or a resistor

and capacitor in parallel) between this pin and GND to limit

the temperature rise of the external pass device.

NDRV (Pin 18): Drive Output for the External Pass Device

of the VCC Linear Regulator. Connect to the base (NPN) or

gate (NMOS) of an external N-type device.

VIN (Pin 19): Connect to a higher voltage bias supply,

typically the output of a peak detected bias winding. When

not used, tie together with the VCC and NDRV pins.

SW (Pin 20): Connect to the drain of the “synchronous”

MOSFET. This input is used for adaptive shoot-through

prevention and leading edge blanking.

PT–, PT+ (Pins 21, 22):

Pulse Transformer Driver Outputs.

For most applications, these connect to a pulse trans-

former (with a series DC blocking capacitor). The PWM

information is multiplexed together with DC power and

sent through a single pulse transformer to the primary

side. This information may be decoded by the LTC3705

gate driver and primary-side controller.

PGND (Pin 23): Gate Driver Ground Pin.

VCC (Pin 24): Main VCC Input for all Driver and Control

Circuitry.

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