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CD74ACT05 Scheda tecnica(PDF) 4 Page - Texas Instruments |
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CD74ACT05 Scheda tecnica(HTML) 4 Page - Texas Instruments |
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4 / 6 page ![]() 4 Switching Specifications Input tr, tf = 3ns, CL = 50pF (Worst Case) PARAMETER SYMBOL VCC (V) -40oC TO 85oC -55oC TO 125oC UNITS MIN TYP MAX MIN TYP MAX AC TYPES Propagation Delay, Input to Output (CD74AC/ACT04) tPLH, tPHL 1.5 - - 74 - - 81 ns 3.3 (Note 9) 2.3 - 8.3 2.3 - 9.1 ns 5 (Note 10) 1.7 - 5.9 1.6 - 6.5 ns Propagation Delay, High Z to Output Low (CD74AC/ACT05) tPZL 1.5 - - 74 - - 81 ns 3.3 2.3 - 8.3 2.3 - 9.1 ns 5 1.7 - 5.9 1.6 - 6.5 ns Propagation Delay, Output Low to High Z (CD74AC/ACT05) tPLZ 1.5 - - 94 - - 103 ns 3.3 3 - 10.4 2.9 - 11.5 ns 5 2.2 - 7.5 2.1 - 8.2 ns Input Capacitance CI - - -10- -10 pF Power Dissipation Capacitance CPD (Note 11) - - 105 - - 105 - pF ACT TYPES Propagation Delay, Input to Output (CD74AC/ACT04) tPLH, tPHL 5 (Note 10) 2.4 - 8.5 2.3 - 9.3 ns Propagation Delay, Output Low to High Z tPLZ 5 2.8 - 9.8 2.7 - 10.8 ns Propagation Delay, High Z to Output Low (CD74AC/ACT05) tPZL 5 2.4 - 8.5 2.3 - 9.3 ns Input Capacitance CI - - -10- -10 pF Power Dissipation Capacitance CPD (Note 11) - - 105 - - 105 - pF NOTES: 8. Limits tested at 100%. 9. 3.3V Min at 3.6V, Max at 3V. 10. 5V Min at 5.5V, Max at 4.5V. 11. CPD is used to determine the dynamic power consumption per gate. AC: PD = VCC 2 f i (CPD + CL) ACT: PD = VCC 2 f i (CPD + CL) + VCC ∆ICC where fi = input frequency, CL = output load capacitance, VCC = supply voltage. DUT OUTPUT RL (NOTE) OUTPUT LOAD 500 Ω CL 50pF NOTE: For AC Series Only: When VCC = 1.5V, RL = 1kΩ. FIGURE 1. PROPAGATION DELAY TIMES CD74AC CD74ACT Input Level VCC 3V Input Switching Voltage, VS 0.5 VCC 1.5V Output Switching Voltage, VS 0.5 VCC 0.5 VCC FIGURE 2. WAVEFORMS INPUT tr tf 90% VS GND OUTPUT tPHL tPLH VS CD74AC04, CD74ACT04, CD74AC05, CD74ACT05 |
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