SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163

SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163

SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS

SDAS276 – DECEMBER 1994

12

POST OFFICE BOX 655303

APPLICATION INFORMATION

n-bit synchronous counters

This application demonstrates how the ripple-mode carry circuit (see Figure 1) and the carry-look-ahead circuit

(see Figure 2) can be used to implement a high-speed n-bit counter. The SN54ALS162B counts in BCD. The

decreases in Figure 1, but remains unchanged in Figure 2.

Figure 1. Ripple-Mode Carry Circuit

Figure 2. Carry-Look-Ahead Circuit

LOAD

C5/T,3,4+

QA

QB

QC

QD

CLR

A

B

C

D

CTR

CT=0

M1

G3

G4

RCO

CLK

ENP

ENT

3CT=MAX

1,5D

LOAD

C5/T,3,4+

QA

QB

QC

QD

CLR

A

B

C

D

CTR

CT=0

M1

G3

G4

RCO

CLK

ENP

ENT

3CT=MAX

1,5D

LOAD

C5/T,3,4+

QA

QB

QC

QD

CLR

A

B

C

D

CTR

CT=0

M1

G3

G4

RCO

CLK

ENP

ENT

3CT=MAX

1,5D

LOAD

C5/T,3,4+

QA

QB

QC

QD

CLR

A

B

C

D

CTR

CT=0

M1

G3

G4

RCO

CLK

ENP

ENT

3CT=MAX

1,5D

LSB

To More Significant Stages

Clear (L)

Count (H)

Disable (L)

Load (L)

Count (H)

Disable (L)

Clock

LOAD

C5/T,3,4+

QA

QB

QC

QD

CLR

A

B

C

D

CTR

CT=0

M1

G3

G4

RCO

CLK

ENP

ENT

3CT=MAX

1,5D

LOAD

C5/T,3,4+

QA

QB

QC

QD

CLR

A

B

C

D

CTR

CT=0

M1

G3

G4

RCO

CLK

ENP

ENT

3CT=MAX

1,5D

LOAD

C5/T,3,4+

QA

QB

QC

QD

CLR

A

B

C

D

CTR

CT=0

M1

G3

G4

RCO

CLK

ENP

ENT

3CT=MAX

1,5D

LOAD

C5/T,3,4+

QA

QB

QC

QD

CLR

A

B

C

D

CTR

CT=0

M1

G3

G4

RCO

CLK

ENP

ENT

3CT=MAX

1,5D

LSB

To More Significant Stages

Clear (L)

Count (H)

Disable (L)

Load (L)

Clock

fmax = 1/(CLK to RCO tPLH) + (ENT to RCO tPLH) (N – 2) + (ENT tsu)fmax = 1/(CLK to RCO tPLH) + (ENP tsu)