CDK1304 datasheet(4/11 Pages) CADEKA

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Data Sheet

Electrical Characteristics

(TA = TMin to TMax, AVDD = DVDD = OVDD = +5V, VIN = 0 to 4V, ƒclk = 25 MSPS, VRHS = 4V, VRLS = 0V; unless otherwise noted)

symbol

parameter

conditions

Min

typ

Max

units

Resolution

bits

DC Performance

DLE

Differential Linearity Error

±0.5

LSB

ILE

Integral Linearity Error

±1.0

LSB

No Missing Codes

Guaranteed

Analog Input

Input Voltage Range(1)

VRLS

VRHS

Input Resistance(2)

kΩ

Input Capacitance

Input Bandwidth

Small Signal

100

MHz

Gain Error

±2.0

LSB

Offset Error

±2.0

LSB

Reference Input

Resistance(1)

300

500

600

Bandwidth

Small Signal

150

MHz

Voltage Range

VRLS(2)

2.0

VRHS(2)

3.0

AVDD

VRHS – VRLS

4.0

Δ (VRHF – VRHS)

Δ (VRLS – VRLF)

Reference Settling Time

VRHS

CLK Cycle

VRLS

CLK Cycle

Conversion Characteristics

Maximum Conversion Rate(1)

MHz

Minimum Conversion Rate(2)

MHz

Pipeline Delay (Latency)(2)

CLK Cycle

Aperture Delay Time

Aperture Jitter Time

pspp

Dynamic Performance

ENOB

Effective Number of Bits

ƒIN = 3.58MHz

8.5

Bits

ƒIN = 10.3MHz

8.3

Bits

SNR

Signal-to-Noise Ratio w/o Harmonics

ƒIN = 3.58MHz(1)

ƒIN = 10.3MHz(1)

THD

Total Harmonic Distortion

ƒIN = 3.58MHz(1) ,

9 distortion bins from 1024 pt FFT

55.5

ƒIN = 10.3MHz(1) ,

9 distortion bins from 1024 pt FFT

51.5

SINAD

Signal-to-Noise and Distortion

ƒIN = 3.58MHz(1)

ƒIN = 10.3MHz(1)

50.5

notes:

1. 100% production tested at +25°C.

2. Parameter is guaranteed (but not tested) by design and characterization data.

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