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LTC2222 Scheda tecnica(PDF) 5 Page - Linear Technology |
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LTC2222 Scheda tecnica(HTML) 5 Page - Linear Technology |
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5 / 28 page ![]() LTC2222/LTC2223 5 22223fa LTC2222 LTC2223 SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS VDD Analog Supply Voltage (Note 7) ● 3.1 3.3 3.5 3.1 3.3 3.5 V OVDD Output Supply Voltage (Note 7) ● 0.5 3.3 3.6 0.5 3.3 3.6 V IVDD Analog Supply Current ● 144 162 111 123 mA PDISS Power Dissipation ● 475 535 366 406 mW PSHDN Shutdown Power SHDN = H, OE = H, No CLK 2 2 mW PNAP Nap Mode Power SHDN = H, OE = L, No CLK 35 35 mW LTC2222 LTC2223 SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS fS Sampling Frequency ● 1 105 1 80 MHz tL ENC Low Time Duty Cycle Stabilizer Off ● 4.5 4.76 500 5.9 6.25 500 ns Duty Cycle Stabilizer On ● 3 4.76 500 3 6.25 500 ns tH ENC High Time Duty Cycle Stabilizer Off ● 4.5 4.76 500 5.9 6.25 500 ns Duty Cycle Stabilizer On ● 3 4.76 500 3 6.25 500 ns tAP Sample-and-Hold Aperture Delay 0 0 ns tD ENC to DATA Delay (Note 7) ● 1.3 2.1 4 1.3 2.1 4 ns tC ENC to CLOCKOUT Delay (Note 7) ● 1.3 2.1 4 1.3 2.1 4 ns DATA to CLOCKOUT Skew (tC - tD) (Note 7) ● –0.6 0 0.6 –0.6 0 0.6 ns tOE Output Enable Delay (Note 7) ● 510 510 ns Pipeline Latency 5 5 Cycles POWER REQUIRE E TS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 8) TI I G CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to ground with GND and OGND wired together (unless otherwise noted). Note 3: When these pin voltages are taken below GND or above VDD, they will be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND or above VDD without latchup. Note 4: VDD = 3.3V, fSAMPLE = 105MHz (LTC2222) or 80MHz (LTC2223), differential ENC+/ENC– = 2VP-P sine wave, input range = 2VP-P with differential drive, unless otherwise noted. Note 5: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 6: Offset error is the offset voltage measured from –0.5 LSB when the output code flickers between 0000 0000 0000 and 1111 1111 1111 in 2’s complement output mode. Note 7: Guaranteed by design, not subject to test. Note 8: VDD = 3.3V, fSAMPLE = 105MHz (LTC2222) or 80MHz (LTC2223), differential ENC+/ENC– = 2VP-P sine wave, input range = 1VP-P with differential drive. |
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