TLV1571 datasheet(21/29 Pages) TI

21 / 29 page

TLV1571, TLV1578

2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,

PARALLEL ANALOG-TO-DIGITAL CONVERTERS

SLAS170C –MARCH 1999 – REVISED FEBRUARY 2000

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

timing requirements, AVDD = DVDD = 5 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

tc(CLK)

Cycle time CLK

DVDD = 4.5 V to 5.5 V

tc(CLK)

Cycle time, CLK

DVDD = 2.7 V to 3.3 V

100

t(sample)

Reset and sampling time

SYSCLK

Cycles

Total conversion time

SYSCLK

Cycles

twL(EOC)

Pulse width, end of conversion, EOC

SYSCLK

Cycles

twL(INT)

Pulse width, interrupt

SYSCLK

Cycles

t(STARTOSC)

Start-up time, internal oscillator

100

td(CSH_ CSTARTL)

Delay time, CS high to CSTART low

ten(RDL DAV)

Enable time data out

DVDD = 5 V at 50 pF

ten(RDL_DAV)

Enable time, data out

DVDD = 3 V at 50 pF

tdis(RDH DAV)

Disable time data out

DVDD = 5 V at 50 pF

tdis(RDH_DAV)

Disable time, data out

DVDD = 3 V at 50 pF

tsu(CSL_WRL)

Setup time, CS to WR

th(WRH_CSH)

Hold time, CS to WR

tw(WR)

Pulse width, write

Clock

Period

tw(RD)

Pulse width, read

Clock

Period

tsu(DAV_WRH)

Setup time, data valid to WR

th(WRH_DAV)

Hold time, data valid to WR

tsu(CSL_RDL)

Setup time, CS to RD

th(RDH_CSH)

Hold time, CS to RD

th(WRL_EXTXLKH)

Hold time WR to clock high

th(RDL_EXTCLKH)

Hold time RD to clock high

th(CSTARTL_EXTCLKH)

Hold time CSTART to clock high

tsu(WRH_EXTCLKH)

Setup time WR high to clock high

tsu(RDH_EXTCLKH)

Setup time RD high to clock high

tsu(CSTARTH_EXTCLKH)

Setup time CSTART high to clock high

td(EXTCLK_CSTARTL)

Delay time clock low to CSTART low

NOTE: Specifications subject to change without notice.

Data valid is denoted as DAV.

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