internal clock

With CS low and WR low, data is written into the ADC. The sampling begins at the falling edge of CSTART, and conversion begins at the rising

edge of CSTART. The internal clock turns on at the rising edge of CSTART. The internal clock is disabled after each conversion.

OR

Auto Powerdown

CS

WR

CSTART

INTCLK

RD

D[0:7]

INT

EOC

Config

Data

ADC

Data

ADC

Data

t

su(CSL_WRL)

th(WRH_CSH)

td(CSH_CSTARTL)

tsu(DAV_WRH)

t

h(WRH_DAV)

tc

tsu(CSL_RDL)

th(RDH_CSH)

ten(RDL_DAV)

tdis(RDH_DAV)

tc

tsu(CSL_RDL)

ten(RDL_DAV)

t

(STARTOSC)

t(STARTOSC)

9

10

1

0

Auto Powerdown

Figure 5. Input Conversion – Hardware CSTART, Internal Clock