TMS320F243 datasheet(76/116 Pages) TI

76 / 116 page

TMS320F243, TMS320F241

DSP CONTROLLERS

SPRS064B – DECEMBER 1997 – REVISED FEBRUARY 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

PARAMETER MEASUREMENT INFORMATION

timing parameter symbology

Timing parameter symbols used are created in accordance with JEDEC Standard 100-A. To shorten the

symbols, some of the pin names and other related terminology have been abbreviated as follows:

A[15:0]

Memory strobe pins IS, DS, or PS

XTAL1/CLKIN

READY

CLKOUT

Read cycle or RD

D[15:0]

RESET pin RS

INT

NMI, XINT1, XINT2

Write cycle or WE

Lowercase subscripts and their meanings:

Letters and symbols and their meanings:

access time

High

cycle time (period)

Low

delay time

Valid

fall time

Unknown, changing, or don’t care level

hold time

High impedance

rise time

setup time

transition time

valid time

pulse duration (width)

general notes on timing parameters

All output signals from the ’F243/’F241 devices (including CLKOUT) are derived from an internal clock such that

all output transitions for a given half-cycle occur with a minimum of skewing relative to each other.

The signal combinations shown in the following timing diagrams may not necessarily represent actual cycles.

For actual cycle examples, refer to the appropriate cycle description section of this data sheet.

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