TMS320UC5409 datasheet(46/74 Pages) TI

46 / 74 page

TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

memory and parallel I/O interface timing (continued)

switching characteristics over recommended operating conditions for a

parallel I/O port read

(IOSTRB = 0)† (see Figure 18)

PARAMETER

MIN

MAX

UNIT

td(CLKL-A)

Delay time, CLKOUT low to address valid

td(CLKH-ISTRBL)

Delay time, CLKOUT high to IOSTRB low

td(CLKH-ISTRBH)

Delay time, CLKOUT high to IOSTRB high

th(A)IOR

Hold time, address after CLKOUT low

† Address and IS timings are included in timings referenced as address.

timing requirements for a

parallel I/O port read (IOSTRB = 0) [H = 0.5 tc(CO)]† (see Figure 18)

MIN

MAX

UNIT

ta(A)IO

Access time, read data access from address valid

3H–10

ta(ISTRBL)IO

Access time, read data access from IOSTRB low

2H–10

tsu(D)IOR

Setup time, read data before CLKOUT high

th(D)IOR

Hold time, read data after CLKOUT high

th(ISTRBH-D)R

Hold time, read data after IOSTRB high

† Address and IS timings are included in timings referenced as address.

R/W

IOSTRB

D[15:0]

A[19:0]

CLKOUT

th(A)IOR

td(CLKH-ISTRBH)

th(D)IOR

tsu(D)IOR

ta(A)IO

td(CLKH-ISTRBL)

td(CLKL-A)

ta(ISTRBL)IO

th(ISTRBH-D)R

Figure 18. Parallel I/O Port Read (IOSTRB = 0)

TMS320UC5409 Scheda tecnica(PDF) 46 Page - Texas Instruments

TMS320UC5409 Scheda tecnica(HTML) 46 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74

Scheda tecnica Scarica

Link URL