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PCS2I99447 Scheda tecnica(PDF) 1 Page - PulseCore Semiconductor

Il numero della parte PCS2I99447
Spiegazioni elettronici  3.3V/2.5V 1:9 LVCMOS Clock Fanout Buffer
PDF  14 Pages
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Produttore elettronici  PULSECORE [PulseCore Semiconductor]
Homepage  http://www.onsemi.com/
Logo PULSECORE - PulseCore Semiconductor

PCS2I99447 Scheda tecnica(HTML) 1 Page - PulseCore Semiconductor

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September 2006
PCS2I99447
rev 0.4
Notice: The information in this document is subject to change without notice.
PulseCore Semiconductor Corporation
1715 S. Bascom Ave Suite 200, Campbell, CA 95008
• Tel: 408-879-9077 • Fax: 408-879-9018
www.pulsecoresemi.com
3.3V/2.5V 1:9 LVCMOS Clock Fanout Buffer
Features
•
9 LVCMOS Compatible Clock Outputs
•
2 Selectable, LVCMOS Compatible Inputs
•
Maximum Clock Frequency of 350 MHz
•
Maximum Clock Skew of 150 pS
•
Synchronous Output Stop in Logic Low State
Eliminates Output Runt Pulses
•
High–Impedance Output Control
•
3.3V or 2.5V Power Supply
•
Drives up to 18 Series Terminated Clock Lines
•
Ambient Temperature Range -40°C to +85°C
•
32 Lead LQFP and TQFP Packaging
•
Supports
Clock
Distribution
in
Networking,
Telecommunications and Computer Applications
•
Pin and Function Compatible to MPC947 and
MPC9447
Functional Description
The PCS2I99447 is a 3.3V or 2.5V compatible, 1:9 clock
fanout buffer targeted for high performance clock tree
applications. With output frequencies up to 350 MHz and
output skews less than 150 pS, the device meets the needs
of most demanding clock applications.
PCS2I99447 is specifically designed to distribute LVCMOS
compatible clock signals up to a frequency of 350 MHz.
Each output provides a precise copy of the input signal with
a near zero skew. The outputs buffers support driving of
50
Ω terminated transmission lines on the incident edge:
each is capable of driving either one parallel terminated or
two series terminated transmission lines.
Two selectable independent LVCMOS compatible clock
inputs are available, providing support of redundant clock
source systems. The PCS2I99447 CLK_STOP control is
synchronous to the falling edge of the input clock. It allows
the start and stop of the output clock signal only in a logic
low state, thus eliminating potential output runt pulses.
Applying the OE control will force the outputs into high
impedance mode.
All inputs have an internal pull–up or pull–down resistor
preventing unused and open inputs from floating. The
device supports a 2.5V or 3.3V power supply and an
ambient temperature range of –40°C to +85°C. The
PCS2I99447
is
pin
and
function
compatible
but
performance enhanced to the MPC947 and MPC9447.


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