Motore di ricerca datesheet componenti elettronici
  Italian  ▼
ALLDATASHEETIT.COM

X  

PCS5I9352 Scheda tecnica(PDF) 7 Page - PulseCore Semiconductor

Il numero della parte PCS5I9352
Spiegazioni elettronici  2.5V or 3.3V, 200MHz, 11 Output Zero Delay Buffer
PDF  12 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Produttore elettronici  PULSECORE [PulseCore Semiconductor]
Homepage  http://www.onsemi.com/
Logo PULSECORE - PulseCore Semiconductor

PCS5I9352 Scheda tecnica(HTML) 7 Page - PulseCore Semiconductor

Back Button PCS5I9352 Datasheet HTML 3Page - PulseCore Semiconductor PCS5I9352 Datasheet HTML 4Page - PulseCore Semiconductor PCS5I9352 Datasheet HTML 5Page - PulseCore Semiconductor PCS5I9352 Datasheet HTML 6Page - PulseCore Semiconductor PCS5I9352 Datasheet HTML 7Page - PulseCore Semiconductor PCS5I9352 Datasheet HTML 8Page - PulseCore Semiconductor PCS5I9352 Datasheet HTML 9Page - PulseCore Semiconductor PCS5I9352 Datasheet HTML 10Page - PulseCore Semiconductor PCS5I9352 Datasheet HTML 11Page - PulseCore Semiconductor Next Button
Zoom Inzoom in Zoom Outzoom out
 7 / 12 page
background image
September 2006
PCS5I9352
rev 0.3
2.5V or 3.3V, 200MHz, 11-Output Zero Delay Buffer
7 of 12
Notice: The information in this document is subject to change without notice.
AC Electrical Specifications (V
DD = 3.3V ± 5%, TA = -40°C to +85°C)
1
Parameter
Description
Condition
Min
Typ
Max
Unit
fVCO
VCO Frequency
200
500
MHz
÷2 Feedback
100
200
÷4 Feedback
50
125
÷6 Feedback
33.33
83.33
÷8 Feedback
25
62.5
÷12 Feedback
16.67
41.67
fin
Input Frequency
Bypass mode
(PLL_EN# = 1)
0
200
MHz
frefDC
Input Duty Cycle
25
75
%
tr, tf
TCLK Input Rise/FallTime
0.8V to 2.0V
1.0
nS
÷2 Output
100
200
÷4 Output
50
125
÷6 Output
33.33
83.33
÷8 Output
25
62.5
fMAX
Maximum Output Frequency
÷12 Output
16.67
41.67
MHz
fMAX< 100MHz
48
52
DC
Output Duty Cycle
fMAX > 100MHz
44
56
%
tr, tf
Output Rise/Fall times
0.55V to 2.4V
0.1
1.0
nS
t(φ)
Propagation Delay
(static phase offset)
TCLK to FB_IN, same VDD,
does not include jitter
-100
200
pS
tsk(O)
Output-to-Output Skew
Skew within each Bank
125
pS
Banks at same voltage,
same frequency
175
Banks at same voltage,
different frequency
235
tsk(B)
Bank-to-Bank Skew
Banks at different voltage
425
pS
tPLZ, HZ
Output Disable Time
8
nS
tPZL, ZH
Output Enable Time
10
nS
÷2 Feedback
2
÷4 Feedback
1 - 1.5
÷6 Feedback
0.6
÷8 Feedback
0.75
BW
PLL Closed Loop Bandwidth (-3dB)
÷12 Feedback
0.5
MHz
Same frequency
100
tJIT(CC)
Cycle-to-Cycle Jitter
Multiple frequencies
275
pS
Same frequency
100
tJIT(PER)
Period Jitter
Multiple frequencies
150
pS
VCO < 300MHz
150
tJIT(φ)
I/O Phase Jitter
VCO > 300MHz
100
pS
tLOCK
Maximum PLL Lock Time
1
mS
Note:1
.AC characteristics apply for parallel output termination of 50Ω to V
TT. Parameters are guaranteed by characterization and are not 100% tested.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12


Scheda tecnica Scarica

Go To PDF Page


Link URL



Lei ha avuto il aiuto da alldatasheet?  [ DONATE ] 

Di alldatasheet   |   Richest di pubblicita   |   contatti   |   Privacy Policy   |   Collegamento alla scheda tecnica    |   scambio Link   |   Ricerca produttore
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com