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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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PCM5310PAPR Scheda tecnica(PDF) 56 Page - Texas Instruments |
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PCM5310PAPR Scheda tecnica(HTML) 56 Page - Texas Instruments |
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56 / 103 page  PCM5310 SLES244 – FEBRUARY 2009 ............................................................................................................................................................................................ www.ti.com RDM4: Read Digital Mute Status for DAC34, R-Channel RDM3: Read Digital Mute Status for DAC34, L-Channel RDM2: Read Digital Mute Status for DAC12, R-Channel RDM1: Read Digital Mute Status for DAC12, L-Channel These bits are used to read the digital soft mute status for each DAC channel through the I2C port. Default value: 1 0 Mute disabled 1 Mute enabled (default) RAM4: Read Digital Mute Status for ADC34, R-Channel RAM3: Read Digital Mute Status for ADC34, L-Channel RAM2: Read Digital Mute Status for ADC12, R-Channel RAM1: Read Digital Mute Status for ADC12, L-Channel These bits are used to read the digital soft mute status for each ADC channel through the I2C port. Default value: 1 0 Mute disabled 1 Mute enabled (default) RRHZR: Read Volume Zero Cross Time Out Status for Headphone, R-Channel RHZL: Read Volume Zero Cross Time Out Status for Headphone, L-Channel RDZ4: Read Digital Attenuation/Mute Zero Cross Timeout Status for DAC34, R-Channel RDZ3: Read Digital Attenuation/Mute Zero Cross Timeout Status for DAC34, L-Channel RDZ2: Read Digital Attenuation/Mute Zero Cross Timeout Status for DAC12, R-Channel RDZ1: Read Digital Attenuation/Mute Zero Cross Timeout Status for DAC12, L-Channel RAZ4: Read Digital Attenuation/Mute Zero Cross Timeout Status for ADC34, R-Channel RAZ3: Read Digital Attenuation/Mute Zero Cross Timeout Status for ADC34, L-Channel RAZ2: Read Digital Attenuation/Mute Zero Cross Timeout Status for ADC12, R-Channel RAZ1: Read Digital Attenuation/Mute Zero Cross Timeout Status for ADC12, L-Channel These bits are used to read the zero-crossing timeout status of digital soft mute and digital attenuation for each ADCs and DACs channel and for headphone output volume through the I2C port. Default value: 0 0 not timed out (default) 1 Timed out CGLD: Glitch Reduction Disable when Changing Clock Source This bit disables the glitch reduction circuit, which reduces audible pop noise when changing the clock input from any SCKx to SCKx. Default value: 0 0 Enabled (default) 1 Disabled 56 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 |
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