THS6214IPWPR datasheet(9/41 Pages) TI

9 / 41 page

THS6214

www.ti.com ....................................................................................................................................................................................................... SBOS431 – MAY 2009

ELECTRICAL CHARACTERISTICS: VS = ±6V (continued)

At TA = +25°C, GDIFF = +5V/V with RL = 100Ω differential load, RADJ = 0Ω, active impedance circuit configuration, and full bias,

unless otherwise noted. Each port is independently tested.

THS6214IRHF, IPWP

TEST

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

LEVEL(1)

LOGIC

Logic 1, with respect to GND(3), TA = –40°C to +85°C

1.9

Bias control pin logic threshold

Logic 0, with respect to GND(3), TA = –40°C to +85°C

0.8

Bias-1, Bias-2 = 0.5V (logic 0)

µA

TA = –40°C to +85°C

µA

Bias pin quiescent current

Bias-1, Bias-2 = 3.3V (logic 1)

0.3

µA

TA = –40°C to +85°C

1.2

µA

Turn-on time delay (tON)

Time for IS to reach 50% of final value

µs

Turn-off time delay (tOFF)

Time for IS to reach 50% of final value

µs

Bias pin input impedance

Ω

Amplifier output impedance

Off bias (Bias-1 = 1, Bias-2 = 1)

10 || 5

Ω || pF

(3)

The GND pin usable range is from VS– to (VS+ – 5V).

Table 1. Logic Table

BIAS-1

BIAS-2

FUNCTION

DESCRIPTION

Full bias mode (100%)

Amplifiers on with lowest distortion possible (default state)

Mid bias mode (75%)

Amplifiers on with power savings and a reduction in distortion performance

Low bias mode (50%)

Amplifiers on with enhanced power savings and a reduction of overall performance

Shutdown mode

Amplifiers off and output has high impedance

Submit Documentation Feedback

Product Folder Link(s): THS6214

THS6214IPWPR Scheda tecnica(PDF) 9 Page - Texas Instruments

THS6214IPWPR Scheda tecnica(HTML) 9 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41

Scheda tecnica Scarica

Link URL