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LPC2919/01 Scheda tecnica(PDF) 25 Page - NXP Semiconductors |
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LPC2919/01 Scheda tecnica(HTML) 25 Page - NXP Semiconductors |
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25 / 86 page ![]() LPC2917_19_01_2 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 02 — 17 June 2009 25 of 86 NXP Semiconductors LPC2917/01; LPC2919/01 ARM9 microcontroller with CAN and LIN A timing diagram for writing to external memory is shown In Figure 6. The relationship between wait-state settings is indicated with arrows. WSTOEN = 3, WST1 = 6 Fig 5. Reading from external memory WSTWEN = 3, WST2 = 7 (1) BLS has the same timing as WE in configurations that use the byte lane enable signals to connect to write enable (8 bit devices). Fig 6. Writing to external memory OE CLK(SYS) CS A D WSTOEN WST1 002aae704 BLS CLK(SYS) CS A D WST2 WSTWEN 002aae705 WE/BLS(1) |
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