5

UCC2585

UCC3585

ISET: A resistor is connected between ISET and ground

to

program

a

precision

bias

for

many

of

the

UCC2585/UCC3585 circuit blocks. Allowable resistor val-

ues are 90k

Ω to 110kΩ. 1.25V is provided to ISET via a

buffered version the internal bandgap voltage reference.

rored directly over to CLSET to program the over current

thresholds. A second use for this current is to set a basis

for the charging current of the oscillator.

PDRV: High current driver output for the high side P

channel MOSFET switch. A 3

Ω to 10Ω series resistor be-

tween PDRV and the MOSFET gate may be inserted to

reduce ringing on this pin. In some layout situations, a

keep the pin from ringing more than 0.5V below ground.

PWRGND: High current return path for the MOSFET

drivers. PWRGND and GND should be terminated to-

gether as close to the IC package as possible.

SD: This pin can configure current limit to operate in any

one of three different ways.

1) A forced voltage of less than 250mV on SD inhibits the

shutdown function causing pulse by pulse limiting.

2) A capacitor from SD to GND provides a control-

ler-converter shutdown timeout after 7 consecutive

overcurrent signals are received by the current limit cir-

cuitry. An interval 10

µA (typ) current source discharges

the SD capacitor to the 0.5V (typ) restart threshold. The

shutdown time is given by:

()

[]

T

CV

A

SHUT

SD

IN

=

•−05

10

.

µ

,

and VIN is the chip supply voltage (on pin 15). At this

point, a softstart cycle is initiated, and a 100

µA current

(typ) quickly recharges SD to VIN. During softstart, pulse

by pulse limiting is enabled, and the 7 cycle count is de-

layed until softstart is complete (i.e. charged to approxi-

mately VIN volts).

3) A forced voltage of greater than 1V on SD will cause

the UCC2585/UCC3585 to latch OFF after 7 overcurrent

signals are received. After the controller is latched off, SD

must drop below 250mV to restart the controller.

SS: A low leakage capacitor connected between SS and

GND will provide a softstart function for the converter.

The voltage on this capacitor will slowly charge on start-

up via an internal current source. The output of the Volt-

age error amplifier (COMP) tracks this voltage thereby

limiting the controller duty ratio.

NDRV: High current driver output for the low side

MOSFET switch. A 3

Ω to 10Ω series resistor between

NDRV and the MOSFET gate may be inserted to reduce

ode may be required from this pin to ground to keep the

pin from ringing more than 0.5V below ground.

TRACK: A resistor is connected between TRACK and

output voltage of the converter to set the start-up profile

of the power converter. Certain dual supply rail micropro-

cessors require that a maximum voltage differential be-

tween the supply rails is not exceeded. Failure to do so

results in large currents in the microprocessor through

the ESD (electrostatic discharge) protection devices. This

can result in chip failure. The UCC2585/UCC3585 is de-

the 2.0V (nom.) UVLO threshold. That is, the high side P

channel MOSFET switch driver output is actively held low

allowing the MOSFET to conduct current to the output as

voltage level on VOUT at which the P channel MOSFET

is turned off. The tracking cutoff voltage follows the fol-

lowing relationship:

()

VV

A

R

OUT

TRACK

(max)

.

=+

•

125

12

µ

This is necessary for very low output voltage applications

(< 2.0V), where overvoltage may occur if the Pchannel

MOSFET is not disabled before the UVLO threshold is

VFB: Inverting input to the Voltage type error amplifier.

The common mode input range for VFB extends from

GND to 1.5V.

VIN: Supply voltage for the UCC2585/UCC3585.Bypass

with a 0.1

µF ceramic capacitor (minimum) to supply the

switching transient currents required by the external

MOSFET switches.

PIN DESCRIPTIONS (cont.)