SPT7852 datasheet(8/11 Pages) CADEKA

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SPT7852

Figure 4 – Ladder Force/Sense Circuit

AGND

VRHF

VRHS

VRLS

VRLF

All capacitors are 0.01 µF

Figure 5 – Simplified Reference Ladder Drive Circuit

Without Force/Sense Circuit

R/2

R=30

Ω (typ)

All capacitors are 0.01 µF

VRLF (AGND)

0.0 V

VRLS

(0.150 V)

VRHS

(+3.85 V)

150 mV

+4.0 V

External

Reference

VOLTAGE REFERENCE

The SPT7852 requires the use of a single external voltage

reference for driving the high side of the reference ladder. It

must be within the range of 3 V to 5 V. Both ADCs share the

same reference ladder. The lower side of the ladder is typi-

cally tied to AGND (0.0 V), but can be run up to 2.0 V with a

second reference. The analog input voltage range will track

the total voltage difference measured between the ladder

sense lines, VRHS and VRLS.

Force and sense taps are provided to ensure accurate and

stable setting of the upper and lower ladder sense line volt-

ages across part-to-part and temperature variations. By us-

ing the configuration shown in figure 4, offset and gain er-

rors of less than

±2 LSB can be obtained.

In cases where wider variations in offset and gain can be

tolerated, VRef can be tied directly to VRHF and AGND can

be tied directly to VRLF as shown in figure 5. Decouple force

and sense lines to AGND with a .01

µF capacitor (chip cap

preferred) to minimize high-frequency noise injection. If this

simplified configuration is used, the following considerations

should be taken into account:

The reference ladder circuit shown in figure 5 is a simplified

representation of the actual reference ladder with force and

sense taps shown. Typically, the top side voltage drop for

VRHF to VRHS will equal:

VRHF – VRHS = 3.75% of (VRHF – VRLF) (typical),

and the bottom side voltage drop for VRLS to VRLF will equal:

VRLS – VRLF = 3.75% of (VRHF – VRLF) (typical).

Figure 5 shows an example of expected voltage drops for a

specific case. VRef of 4.0 V is applied to VRHF and VRLF is

tied to AGND. A 150 mV drop is seen at VRHS (= 3.85 V) and

a 150 mV increase is seen at VRLS (= 0.150 V).

ANALOG INPUT

VINA and VINB are the analog inputs for channel A and chan-

nel B, respectively. Both channels share the same refer-

ence ladder. The input voltage range is from VRLS to VRHS

(typically 4.0 V) and will scale proportionally with respect to

the voltage reference. (See voltage reference section.)

The drive requirements for the analog inputs are very mini-

mal when compared to most other converters due to the

SPT7852’s extremely low input capacitance of only 5 pF

and very high input resistance of 50 k

Ω.

The analog input should be protected through a series resis-

tor and diode clamping circuit as shown in figure 6.

Figure 6 – Recommended Input Protection Circuit

Ω

ADC

Buffer

AVDD

-V

D1 = D2 = Hewlett Packard HP5712 or equivalent

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