SPT7853 datasheet(10/10 Pages) CADEKA

10 / 10 page

12/14/99

SPT7853

PIN ASSIGNMENTS

PART NUMBER

TEMPERATURE RANGE

PACKAGE TYPE

SPT7853SCT

0 to +70

°C

52-Pin TQFP

ORDERING INFORMATION

Name

Function

VINA

Analog input for channel A

VINB

Analog input for channel B

VINC

Analog input for channel C

DA0–DA9 CMOS-compatible digital output data for channel A

(+2.7 V to +5.0 voltage logic)

DB0–DB9 CMOS-compatible digital output data for channel B

(+2.7 V to +5.0 voltage logic)

DC0–DC9 CMOS-compatible digital output data for channel C

(+2.7 V to +5.0 voltage logic)

OEN

Output enable pin. (Low = enabled; High = high

impedance)

CLK

CMOS-compatible input clock (2x of sample rate).

VRHF

Input for top of reference ladder (force)

VRHS

Input for top of reference ladder (sense)

VRLF

Input for bottom of reference ladder (force)

VRLS

Input for bottom of reference ladder (sense)

VDD

Analog +5 V; Digital +5 V

OVDD

Output supply +2.7 / +5 V

AGND

Analog ground

DGND

Digital ground

VRLT

Tie to VRLS

VCAL

Calibration reference

DAV

Data available

PIN FUNCTIONS

VRHS

VRLF

VRLS

VRLT

AGND

VINA

AGND

VINB

VDD

VCAL

AGND

VINC

AGND

CLK

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

DAV

OVDD

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