TMC2193 datasheet(39/72 Pages) CADEKA

39 / 72 page

PRODUCT SPECIFICATION

TMC2193

REV. 1.0 3/26/03

Control Register Deﬁnitions (continued)

Input Format Register (0x05)

76543210

D10FF

INMODE

OMIX

SOURCE

Reg

Bit

Name

Description

D1OFF

YCBCR Input Formatting.

When D1OFF is HIGH, 64 is subtracted from Y data path of the PD port.

When D1OFF is LOW, pixel data is passed through.

6-4

INMODE

Input Mode Select.

000

24 bit GBR

PD[7:0] = G PD[23:16] = B PD[15:8] = R

100

24 bit YCBCR (4:4:4)

PD[7:0] = Y PD[23:16] = CB PD[15:8] = CR

101

10 bit D1 (YCBCR)

PD[23:14] = YCBCR at 27MHz

110

20 bit YCBCR (4:4:4)

PD[9:0] = Y PD[23:14] = CBCR (at 27MHz)

111

20 bit YCBCR (4:2:2)

PD[9:0] = Y PD[23:14] = CBCR

3-2

OMIX

Overlay Mixer Select.

No mix – PD data is always passed

Hard mix – mixer performs a hard switch between PD and Overlay

Set1 mix – the pixel data has the following weighting on the

transition; 0, 1/2, 1

Set2 mix – the pixel data has the following weighting on the

transition; 0, 1/8, 1/2, 7/8, 1

1-0

SOURCE

Video Input Select. Chooses from internal test patterns or pixel data port.

PD PORT

Modulated Ramp

INTERNAL COLOR BAR (75%)

INTERNAL COLOR BAR (100%)

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