F25L32PA datasheet(9/36 Pages) ESMT

9 / 36 page

ESMT

F25L32PA

Elite Semiconductor Memory Technology Inc.

Publication Date: Mar. 2009

Revision: 1.0

9/36

STATUS REGISTER

The software status register provides status on whether the flash

memory array is available for any Read or Write operation,

whether the device is Write enabled, and the state of the memory

Write protection. During an internal Erase or Program operation,

the status register may be read only to determine the completion

of an operation in progress. Table 2 describes the function of

each bit in the software status register.

Table 2: Software Status Register

Bit

Name

Function

Default at

Power-up

Read/Write

Status Register

BUSY

1 = Internal Write operation is in progress

0 = No internal Write operation is in progress

WEL

1 = Device is memory Write enabled

0 = Device is not memory Write enabled

BP0

Indicate current level of block write protection (See Table 3)

R/W

BP1

Indicate current level of block write protection (See Table 3)

R/W

BP2

Indicate current level of block write protection (See Table 3)

R/W

RESERVED Reserved for future use

N/A

RESERVED Reserved for future use

N/A

BPL

1 = BP2,BP1,BP0 are read-only bits

0 = BP2,BP1,BP0 are read/writable

R/W

Note:

1. Only BP0, BP1, BP2 and BPL are writable.

2. All register bits are volatility

3. All area are protected at power-on (BP2=BP1=BP0=1)

WRITE ENABLE LATCH (WEL)

The Write-Enable-Latch bit indicates the status of the internal

memory Write Enable Latch. If this bit is set to “1”, it indicates the

device is Write enabled. If the bit is set to “0” (reset), it indicates

the device is not Write enabled and does not accept any memory

Write (Program/ Erase) commands. This bit is automatically reset

under the following conditions:

• Power-up

• Write Disable (WRDI) instruction completion

• Page Program instruction completion

• Sector Erase instruction completion

• Block Erase instruction completion

• Chip Erase instruction completion

• Write Status Register instructions

BUSY

The BUSY bit determines whether there is an internal Erase or

Program operation in progress. A “1” for the BUSY bit indicates

the device is busy with an operation in progress. A “0” indicates

the device is ready for the next valid operation.

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