CS3001

CS3002

DS490F9

11

The loop gain plot shown in Figure 18 illustrates

the unity gain configuration, and indicates how this

is modified when using the amplifier in a higher

gain configuration with compensation. If it is con-

figured for higher gain, for example, 60 dB, the

x–axis will move up by 60 dB (line B). Capacitor

C2 adds a zero and a pole. The modified plot indi-

cates the effects of introducing the pole and zero

due to capacitor C2. The pole can be located at any

frequency higher than the hand-over frequency, the

zero has to be at a frequency lower than the hand-

over frequency so as to provide adequate gain mar-

gin. The separation between the pole and the zero

occurs at the intersection of the –100 dB/decade

and –80 dB/decade slopes. The point X in the fig-

ure should be at closed loop gain plus 20 dB gain

margin. The value for C2 = 1/(2

π R1 P1). Setting

the pole of the filter to P1 = 1 MHz works very well

and is independent of gain. As the closed loop gain

is changed, the zero location is also modified if R1

remains fixed. Capacitor C2 can be increased in

value to limit the amplifier’s rising noise above

2kHz.

-100 dB/dec

-80 dB/dec

z

1

p

1

Margin

-20 dB/dec

50kHz

1MHz

5MHz

Desired Closed

Loop Gain

X

FREQUENCY

B

Figure 18. Loop Gain Plot: Unity Gain and with Pole-zero Compensation