CS5505-ASZ datasheet(27/40 Pages) CIRRUS

27 / 40 page

PIN DESCRIPTIONS

Pin numbers for four channel devices are in parentheses.

Clock Generator

XIN; XOUT - Crystal In; Crystal Out, Pins 4 (5) and 5 (6).

A gate inside the chip is connected to these pins and can be used with a crystal to provide the

master clock for the device.

Alternatively, an external (CMOS compatible) clock can be

supplied into the XIN pin to provide the master clock for the device. Loss of clock will put the

device into a lower powered state (approximately 70% power reduction).

Serial Output I/O

M/SLP - Serial Interface Mode Select/ Sleep, Pin 6 (7).

Dual function pin which selects the operating mode of the serial port and provides a very low

power sleep function. When M/SLP is tied to the VD+ pin the serial port will operate in the

Synchronous Self-Clocking (SSC) mode. When M/SLP is tied to the DGND pin the serial port

will operate in the Synchronous External Clocking (SEC) mode.

When the M/SLP pin is tied

half way between VD+ and DGND the chip will enter into a very low powered sleep mode in

which its calibration data will be maintained.

CS - Chip Select, Pin 1 (2).

This input allows an external device to access the serial port.

DRDY - Data Ready, Pin 20 (23)

Data Ready goes low at the end of a digital filter convolution cycle to indicate that a new

output word has been placed into the serial port. DRDY will return high after all data bits are

shifted out of the serial port or two master clock cycles before new data becomes available if

the CS pin is inactive (high).

SDATA - Serial Data Output, Pin 19 (22).

SDATA is the output pin of the serial output port. Data from this pin will be output at a rate

determined by SCLK and in a format determined by the M/SLP pin. Data is output MSB first

and advances to the next data bit on the falling edges of SCLK. SDATA will be in a high

impedance state when not transmitting data.

SCLK - Serial Clock Input/Output, Pin 18 (21).

A clock signal on this pin determines the output rate of the data from the SDATA pin. The

M/SLP pin determines whether SCLK is an input or and output. When used as an input, it must

not be allowed to float.

CS5505/6/7/8

DS59F4

CS5505/6/7/8

DS59F6

CS5505-ASZ Scheda tecnica(PDF) 27 Page - Cirrus Logic