AS8SLC128K32P-25LSLASHIT datasheet(5/10 Pages) AUSTIN

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AS8SLC128K32

AustinSemiconductor,Inc.reservestherighttochangeproductsorspecificationswithoutnotice.

AS8SLC128K32

Rev. 0.6 06/05

Austin Semiconductor, Inc.

LOW V

CC DATA RETENTION WAVEFORM

LOW POWER CHARACTERISTICS (L Version Only)

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DATA RETENTION MODE

4.5V

DR > 2V

tCDR

CS\ 1-4

DESCRIPTION

SYMBOL

MIN

MAX

UNITS

NOTES

VCC for Retention Data

VDR

VCC = 2V

ICCDR

VCC = 3V

ICCDR

Chip Deselect to Data

Retention Time

tCDR

0ns

Operation Recovery Time

4, 11

Data Retention Current

All Inputs @ Vcc + 0.2V

or Vss + 0.2V,

CS\ = Vcc + 0.2V

CONDITIONS

HZCS, is less than tLZCS, and tHZWE is less than tLZWE.

8. WE\ is HIGH for READ cycle.

9. Device is continuously selected. Chip selects and output

enable are held in their active state.

10. Address valid prior to or coincident with latest

oc-

curring chip enable.

11. t

RC= READ cycle time.

12. Chip enable (CS\) and write enable (WE\) can initiate and

terminate a WRITE cycle.

13. I

CC is for full 32 bit mode.

NOTES

1. All voltages referenced to V

SS (GND).

2. Worst case address switching.

3. ICC is dependent on output loading and cycle rates.

The specified value applies with the outputs

4. This parameter guaranteed but not tested.

5. Test conditions as specified with output loading as

shown in Fig. 1 & 2 unless otherwise noted.

6. t

HZCS, tHZOE and tHZWE are specified with CL= 5pF as in

Fig.

2. Transition is measured +/- 200 mV typical from steady

state voltage, allowing for actual tester RC time constant.

7. At any given temperature and voltage condition,

RC(MIN)

unloaded, and f=

HZ.

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