AD9572ACPZLVD-R7 datasheet(5/20 Pages) AD

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AD9572

Rev. 0 | Page 5 of 20

LVPECL CLOCK OUTPUT JITTER

Typical (typ) is given for VS = 3.3 V, TA = 25°C, unless otherwise noted.

Table 3.

Jitter Integration

Bandwidth (Typ)

100 MHz

33M = Off/On

106.25 MHz

33M = Off/On

125 MHz

33M = Off/On

156.25 MHz

33M = Off/On

Unit

Test Conditions/Comments

12 kHz to 20 MHz

608/564

418/451

444/2200

420/461

fS rms

LVPECL output frequency combinations

are 1 × 156.25 MHz, 1 × 100 MHz, 1 ×

125 MHz, 2 × 106.25 MHz

1.875 MHz to

20 MHz

200/277

fS rms

LVPECL output frequency combinations

are 1 × 156.25 MHz, 1 × 100 MHz, 1 ×

125 MHz, 2 × 106.25 MHz

637 kHz to 10 MHz

227/232

fS rms

LVPECL output frequency combinations

are 1 × 156.25 MHz, 1 × 100 MHz, 1 ×

125 MHz, 2 × 106.25 MHz

200 kHz to 10 MHz

337/378

242/2200

fS rms

LVPECL output frequency combinations

are 1 × 156.25 MHz, 1 × 100 MHz, 1 ×

125 MHz, 2 × 106.25 MHz

12 kHz to 35 MHz

523 (off only)

fS rms

LVPECL output frequency combinations

are 1 × 156.25 MHz, 2 × 125 MHz, 2 ×

106.25 MHz

CMOS CLOCK OUTPUT JITTER

Typical (typ) is given for VS = 3.3 V, TA = 25°C, unless otherwise noted.

Table 4.

Jitter Integration Bandwidth

25 MHz

33.3 MHz

Unit

Test Conditions/Comments

12 kHz to 5 MHz

781

417

fS rms

200 kHz to 5 MHz

764

524

fS rms

REFERENCE INPUT

Typical (typ) is given for VS = 3.3 V ± 10%, TA = 25°C, unless otherwise noted. Minimum (min) and maximum (max) values are given

over full VS and TA (−40°C to +85°C) variation.

Table 5.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

CLOCK INPUT (REFCLK)

Input Frequency

MHz

Input High Voltage

2.0

Input Low Voltage

0.8

Input Current

−1.0

+1.0

μA

Input Capacitance

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