ADL5562ACPZ-R7 datasheet(15/24 Pages) AD

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ADL5562

Rev. A | Page 15 of 24

INPUT AND OUTPUT INTERFACING

The ADL5562 can be configured as a differential-input to

differential-output driver, as shown in Figure 32. The differential

broadband input is provided by the ETC1-1-13 balun transformer,

and the two 34.8 Ω resistors provide a 50 Ω input match for the

three input impedances that change with the variable gain

strapping. The input and output 0.1 μF capacitors isolate the VCC/2

bias from the source and balanced load. The load should equal 200 Ω

to provide the expected ac performance (see the Specifications

section and the Typical Performance Characteristics section).

3.3V

VIP2

VIP1

VIN1

VIN2

50Ω

0.1µF

ETC1-1-13

0.1µF

NOTES

1. FOR 6dB GAIN (AV = 2), CONNECT INPUT A TO VIP1 AND INPUT B TO VIN1.

2. FOR 12dB GAIN (AV = 4), CONNECT INPUT A TO VIP2 AND INPUT B TO VIN2.

3. FOR 15.5dB GAIN (AV = 6), CONNECT INPUT A TO BOTH VIP1 AND VIP2

AND INPUT B TO BOTH VIN1 AND VIN2.

Figure 32. Differential-Input to Differential-Output Configuration

Table 4. Differential Termination Values for Figure 32

Gain (dB)

R1 (Ω)

R2 (Ω)

28.7

33.2

15.5

40.2

The differential gain of the ADL5562 is dependent on the

source impedance and load, as shown in Figure 33.

200Ω

400Ω

200Ω

100Ω

VIP2

VIP1

VIN1

VIN2

5Ω

0.1µF

1/2 RS

0.1µF

Figure 33. Differential Input Loading Circuit

The differential gain can be determined using the following

formula. The values of RIN for each gain configuration are

shown in Table 5.

400

(1)

Table 5. Values of RIN for Differential Gain

Gain (dB)

RIN (Ω)

200

100

15.5

66.7

Single-Ended Input to Differential Output

The ADL5562 can also be configured in a single-ended input

to differential output driver, as shown in Figure 34. In this

configuration, the gain of the part is reduced due to the application

of the signal to only one side of the amplifier. The strappable

gain values are listed in Table 6 with the required terminations

to match to a 50 Ω source using R1 and R2. Note that R1 must

equal the parallel value of the source and R2. The input and

output 0.1 μF capacitors isolate the VCC/2 bias from the source

and the balanced load. The performance for this configuration

is shown in Figure 11, Figure 14, and Figure 20.

VIP2

VIP1

VIN1

VIN2

50Ω

0.1µF

3.3V

NOTES

1. FOR 5.6dB GAIN (AV = 1.9), CONNECT INPUT A TO VIP1

AND INPUT B TO VIN1.

2. FOR 11.1dB GAIN (AV = 3.6), CONNECT INPUT A TO VIP2

AND INPUT B TO VIN2.

3. FOR 14.1dB GAIN (AV = 5.1), CONNECT INPUT A TO BOTH

VIP1 AND VIP2 AND INPUT B TO BOTH VIN1 AND VIN2.

0.1µF

Figure 34. Single-Ended Input to Differential Output Configuration

Table 6. Single-Ended Termination Values for Figure 34

Gain (dB)

R1 (Ω)

R2 (Ω)

5.6

11.1

14.1

The single-ended gain configuration of the ADL5562 is dependent

on the source impedance and load, as shown in Figure 35.

200Ω

400Ω

200Ω

100Ω

VIP2

VIP1

VIN1

VIN2

5Ω

0.1µF

Figure 35. Single-Ended Input Loading Circuit

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