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STM8L101F2P3 Scheda tecnica(PDF) 55 Page - STMicroelectronics |
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STM8L101F2P3 Scheda tecnica(HTML) 55 Page - STMicroelectronics |
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55 / 77 page ![]() STM8L101xx Electrical parameters Doc ID 15275 Rev 7 55/77 Figure 31. Typical NRST pull-up current Ipu vs VDD @ 4 temperatures The reset network shown in Figure 32 protects the device against parasitic resets. The user must ensure that the level on the NRST pin can go below the VIL max. level specified in Table 30. Otherwise the reset is not taken into account internally. Figure 32. Recommended NRST pin configuration ai17006 0 20 40 60 80 100 120 1.65 1.8 1.95 2.1 2.25 2.4 2.55 2.7 2.85 3 3.15 3.3 3.45 3.6 V DD [V] -40°C 25°C 85°C 125°C 0.01 μF EXTERNAL RESET CIRCUIT STM8L Filter RPU VDD INTERNAL RESET RSTIN |
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