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MPC8377ECVRALGA Scheda tecnica(PDF) 71 Page - Freescale Semiconductor, Inc |
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MPC8377ECVRALGA Scheda tecnica(HTML) 71 Page - Freescale Semiconductor, Inc |
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71 / 124 page  MPC8377E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 71 Serial ATA (SATA) 16.3.2 Gen2i/3G Receiver (Rx) Specifications Table 60 provides the Gen2i or 3 Gbits/s differential receiver input DC characteristics for the SATA interface. Table 61 provides the differential receiver output AC characteristics for the SATA interface at Gen2i or 3.0 Gbits/s transmission. Deterministic jitter, data-data 250 UI USATA_TXDJ250UI — — 0.35 UIp-p 1 Note: 1 Measured at Tx output pins peak to peak phase variation, random data pattern. Table 60. Gen2i/3G Receiver Input DC Specifications Parameter Symbol Min Typical Max Units Notes Differential input voltage VSATA_RXDIFF 275 500 750 mVp-p 1 Differential RX input impedance ZSATA_RXSEIM 85 100 115 Ω — Note: 1 Voltage relative to common of either signal comprising a differential pair. Table 61. Gen 2i/3G Receiver AC Specifications Parameter Symbol Min Typical Max Units Notes Channel Speed tCH_SPEED —3.0 — Gbps — Unit Interval TUI 333.2 333.33 335.11 ps — Total jitter fC3dB =fBAUD/10 USATA_TXTJfB/10 — — 0.46 UIp-p 1 Total jitter fC3dB =fBAUD/500 USATA_TXTJfB/500 — — 0.60 UIp-p 1 Total jitter fC3dB =fBAUD/1667 USATA_TXTJfB/1667 — — 0.65 UIp-p 1 Deterministic jitter fC3dB =fBAUD/10 USATA_TXDJfB/10 — — 0.35 UIp-p 1 Deterministic jitter fC3dB =fBAUD/500 USATA_TXDJfB/500 — — 0.42 UIp-p 1 Deterministic jitter fC3dB =fBAUD/1667 USATA_TXDJfB/1667 — — 0.35 UIp-p 1 Note: 1 Measured at Tx output pins peak to peak phase variation, random data pattern. Table 59. Gen 1i/1.5G Receiver AC Specifications (continued) Parameter Symbol Min Typical Max Units Notes |
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