AD6657EBZ datasheet(29/32 Pages) AD

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AD6657

Rev. 0 | Page 29 of 32

Addr.

(Hex)

Name

(MSB)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

(LSB)

Bit 0

Default

Value

(Hex)

Comments

0x24

BIST signature

LSB (local)

BIST Signature[7:0]

0x00

Read only.

0x25

BIST signature

MSB (local)

BIST Signature[15:8]

0x00

Read only.

Digital Feature Control Registers

0x3A

Sync control

(global)

Open

Clock

divider

sync

enable

0 = off

1 = on

Master

sync

enable

0 = off

1 = on

0x00

Control

synchronize

the clock

divider.

0x3C

NSR control

(local)

Open

MODE

pin disable

0 = MODE

pin used

1 = MODE

pin dis-

abled

NSR mode

000 = 22% BW mode

001 = 33% BW mode

NSR

enable

0 = off

1 = on

(used

only if

Bit 4 = 1;

otherwise

ignored)

0x00

Noise

shaping

requantizer

(NSR)

controls.

0x3E

NSR tuning

word (local)

Open

NSR tuning word

See the Noise Shaping Requantizer (NSR) section.

Equations for the tuning word are dependent on the NSR mode.

0x1C

NSR

frequency

tuning word.

MEMORY MAP REGISTER DESCRIPTIONS

For additional information about functions controlled

in Register 0x00 to Register 0xFF, see Application Note

AN-877, Interfacing to High Speed ADCs via SPI.

Sync Control (Register 0x3A)

Bits[7:2]—Reserved

Bit 1—Clock Divider Sync Enable

Bit 1 gates the sync pulse to the clock divider. The sync signal is

enabled when Bit 1 is high and Bit 0 is high. This is continuous

sync mode.

Bit 0—Master Sync Enable

Bit 0 must be high to enable any of the sync functions. If

the sync capability is not used, this bit should remain low

to conserve power.

NSR Control (Register 0x3C)

Bits[7:5]—Reserved

Bit 4—MODE Pin Disable

Bit 4 specifies whether the selected channels will be controlled

by the MODE pin. Local registers act on the channels that are

selected by the channel index register (Address 0x05).

Bits[3:1]— NSR Mode

Bits[3:1] determine the bandwidth mode of the NSR. When

Bits[3:1] are set to 000, the NSR is configured for a 22% BW

mode that provides enhanced SNR performance over 22% of

the sample rate. When Bits[3:1] are set to 001, the NSR is con-

figured for a 33% BW mode that provides enhanced SNR

performance over 33% of the sample rate.

Bit 0—NSR Enable

The NSR is enabled when Bit 0 is high and disabled when Bit 0

is low. Bit 0 is ignored unless the MODE pin disable bit (Bit 4)

is set.

NSR Tuning Word (Register 0x3E)

Bits[7:6]—Reserved

Bits[5:0]— NSR Tuning Word

The NSR tuning word sets the band edges of the NSR band. In

22% BW mode, there are 57 possible tuning words; in 33% BW

mode, there are 34 possible tuning words. For either mode, each

step represents 0.5% of the ADC sample rate. For the equations

used to calculate the tuning word based on the BW mode of

operation, see the Noise Shaping Requantizer (NSR) section.

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